Add initial pinctrl implementation for RT1062 #41810
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| /* | ||
| * Copyright (c) 2022, NXP | ||
| * SPDX-License-Identifier: Apache-2.0 | ||
| * | ||
| * Generated by rt_cfg_utils.py on 2022-01-19 | ||
| */ | ||
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| #include <nxp/nxp_imx/rt/mimxrt1062-pinctrl.dtsi> | ||
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| &IOMUXC_GPIO_AD_B0_12_LPUART1_TX { | ||
| bias-bus-hold; | ||
| input-enable; | ||
| }; | ||
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| &IOMUXC_GPIO_AD_B0_13_LPUART1_RX { | ||
| bias-bus-hold; | ||
| }; | ||
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| &IOMUXC_GPIO_AD_B1_09_SAI1_MCLK { | ||
| bias-bus-hold; | ||
| input-enable; | ||
| }; | ||
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| &IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 { | ||
| bias-bus-hold; | ||
| input-enable; | ||
| }; | ||
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| &IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 { | ||
| bias-bus-hold; | ||
| input-enable; | ||
| }; | ||
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| &IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK { | ||
| bias-bus-hold; | ||
| input-enable; | ||
| }; | ||
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| &IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC { | ||
| bias-bus-hold; | ||
| input-enable; | ||
| }; | ||
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| # Copyright (c) 2021 NXP | ||
| # SPDX-License-Identifier: Apache-2.0 | ||
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| config PINCTRL_MCUX_RT | ||
| bool "Pin controller driver for MCUX RT1xxx MCUs" | ||
| depends on SOC_SERIES_IMX_RT | ||
| default y | ||
| help | ||
| Enable pin controller driver for NXP RT series MCUs |
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| @@ -0,0 +1,81 @@ | ||
| /* | ||
| * Copyright (c) 2021 NXP | ||
| * | ||
| * SPDX-License-Identifier: Apache-2.0 | ||
| */ | ||
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| #include <drivers/pinctrl.h> | ||
| #include <soc.h> | ||
| #include <fsl_iomuxc.h> | ||
| #include <fsl_gpio.h> | ||
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| int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, | ||
| uintptr_t reg) | ||
| { | ||
| /* configure all pins */ | ||
| for (uint8_t i = 0U; i < pin_cnt; i++) { | ||
| uint32_t mux_register = pins[i].pinmux.mux_register; | ||
| uint32_t mux_mode = pins[i].pinmux.mux_mode; | ||
| uint32_t input_register = pins[i].pinmux.input_register; | ||
| uint32_t input_daisy = pins[i].pinmux.input_daisy; | ||
| uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags; | ||
| volatile uint32_t *config_register = (uint32_t *)pins[i].pinmux.config_register; | ||
| uint32_t config_val = *config_register; | ||
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| IOMUXC_SetPinMux(mux_register, mux_mode, input_register, | ||
| input_daisy, (uint32_t)config_register, | ||
| MCUX_RT_INPUT_ENABLE(pin_ctrl_flags)); | ||
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| if (MCUX_RT_INPUT_SCHMITT_ENABLE(pin_ctrl_flags)) { | ||
| config_val |= IOMUXC_SW_PAD_CTL_PAD_HYS(1); | ||
| } | ||
| if (MCUX_RT_DRIVE_OPEN_DRAIN(pin_ctrl_flags)) { | ||
| config_val |= IOMUXC_SW_PAD_CTL_PAD_ODE(1); | ||
| } | ||
| if (MCUX_RT_BIAS_BUS_HOLD(pin_ctrl_flags)) { | ||
| /* Set pull keeper select to keeper, and pull keeper enable to 1 */ | ||
| config_val |= IOMUXC_SW_PAD_CTL_PAD_PKE(1); | ||
| config_val &= ~IOMUXC_SW_PAD_CTL_PAD_PUE_MASK; | ||
| } | ||
| if (MCUX_RT_BIAS_PULL_DOWN(pin_ctrl_flags)) { | ||
| /* Set pull keeper select to pull, and pull keeper enable to 1 */ | ||
| config_val |= IOMUXC_SW_PAD_CTL_PAD_PKE(1) | IOMUXC_SW_PAD_CTL_PAD_PUE(1); | ||
| /* Set PUS to 0b00 to select pulldown resistor */ | ||
| config_val &= ~IOMUXC_SW_PAD_CTL_PAD_PUS_MASK; | ||
| } | ||
| if (MCUX_RT_BIAS_PULL_UP(pin_ctrl_flags)) { | ||
| /* Set pull keeper select to pull, and pull keeper enable to 1 */ | ||
| config_val |= IOMUXC_SW_PAD_CTL_PAD_PKE(1) | IOMUXC_SW_PAD_CTL_PAD_PUE(1); | ||
| /* Set PUS field to selected value */ | ||
| config_val = ((config_val & ~IOMUXC_SW_PAD_CTL_PAD_PUS_MASK) | | ||
| IOMUXC_SW_PAD_CTL_PAD_PUS(MCUX_RT_BIAS_PULL_UP(pin_ctrl_flags))); | ||
| } | ||
| /* Set drive strength field */ | ||
| config_val = ((config_val & ~IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) | | ||
| IOMUXC_SW_PAD_CTL_PAD_DSE(MCUX_RT_DRIVE_STRENGTH(pin_ctrl_flags))); | ||
| /* Set speed field */ | ||
| config_val = ((config_val & ~IOMUXC_SW_PAD_CTL_PAD_SPEED_MASK) | | ||
| IOMUXC_SW_PAD_CTL_PAD_SPEED(MCUX_RT_SPEED(pin_ctrl_flags))); | ||
| /* Set slew rate field */ | ||
| config_val = ((config_val & ~IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) | | ||
| IOMUXC_SW_PAD_CTL_PAD_SRE(MCUX_RT_SLEW_RATE(pin_ctrl_flags))); | ||
| /* Write out config value */ | ||
| *config_register = config_val; | ||
| } | ||
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| return 0; | ||
| } | ||
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| static int mcux_pinctrl_init(const struct device *dev) | ||
| { | ||
| ARG_UNUSED(dev); | ||
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| CLOCK_EnableClock(kCLOCK_Iomuxc); | ||
| CLOCK_EnableClock(kCLOCK_IomuxcSnvs); | ||
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| return 0; | ||
| } | ||
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| SYS_INIT(mcux_pinctrl_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); |
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Do you need this line? If it's going into the boards directory like this, I guess it will be maintained by hand from now on; it's not clear why the comment that it was generated is relevant.