Alternative pin group based pinctrl implementation for RT1062

boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2022, NXP
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Generated by rt_cfg_utils.py on 2022-03-02
+ */
+
+#include <nxp/nxp_imx/rt/mimxrt1062-iomuxc.dtsi>
+
+&pinctrl {
+	lpuart1_default: lpuart1_default {
+		group0 {
+			pinmux = <&iomuxc_gpio_ad_b0_12_lpuart1_tx
+				&iomuxc_gpio_ad_b0_13_lpuart1_rx>;
+			drive-strength = "r0-6";
+			slew-rate = "slow";
+			nxp,speed = "100-mhz";
+		};
+	};
+
+	lpuart1_sleep: pinmux_lpuart1_sleep {
+		group0 {
+			pinmux = <&iomuxc_gpio_ad_b0_13_gpio1_io13>;
+			bias-disable;
+			drive-strength = "r0";
+			bias-pull-up;
+			bias-pull-up-value = "100k";
+			slew-rate = "slow";
+			nxp,speed = "50-mhz";
+		};
+		group1 {
+			pinmux = <&iomuxc_gpio_ad_b0_12_lpuart1_tx>;
+			drive-strength = "r0-6";
+			slew-rate = "slow";
+			nxp,speed = "100-mhz";
+		};
+	};
+
+	sai1_default: sai1_default {
+		group0 {
+			pinmux = <&iomuxc_gpio_ad_b1_09_sai1_mclk
+				&iomuxc_gpio_ad_b1_13_sai1_tx_data00
+				&iomuxc_gpio_ad_b1_12_sai1_rx_data00
+				&iomuxc_gpio_ad_b1_14_sai1_tx_bclk
+				&iomuxc_gpio_ad_b1_15_sai1_tx_sync>;
+			drive-strength = "r0-6";
+			slew-rate = "slow";
+			nxp,speed = "100-mhz";
+			input-enable;
+		};
+	};
+
+};

boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts

@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include <nxp/nxp_rt1060.dtsi>
+#include "mimxrt1060_evk-pinctrl.dtsi"
 
 / {
 	model = "NXP MIMXRT1060-EVK board";
@@ -175,6 +176,9 @@ arduino_serial: &lpuart3 {};
 &lpuart1 {
 	status = "okay";
 	current-speed = <115200>;
+	pinctrl-0 = <&lpuart1_default>;
+	pinctrl-1 = <&lpuart1_sleep>;
+	pinctrl-names = "default", "sleep";
 };
 
 &enet {
@@ -229,6 +233,8 @@ zephyr_udc0: &usb1 {
 
 &sai1 {
 	status = "okay";
+	pinctrl-0 = <&sai1_default>;
+	pinctrl-names = "default";
 };
 
 /* Enable GPT for use as a hardware timer. This disables Cortex Systick.
@@ -237,3 +243,7 @@ zephyr_udc0: &usb1 {
 &gpt_hw_timer {
 	status = "okay";
 };
+
+&iomuxcgpr {
+	status = "okay";
+};

boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig

@@ -13,3 +13,4 @@ CONFIG_SERIAL=y
 CONFIG_GPIO=y
 CONFIG_ARM_MPU=y
 CONFIG_HW_STACK_PROTECTION=y
+CONFIG_PINCTRL=y

boards/arm/mimxrt1060_evk/pinmux.c

@@ -114,22 +114,6 @@ static int mimxrt1060_evk_init(const struct device *dev)
 	IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0);
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) && CONFIG_SERIAL
-	/* LPUART1 TX/RX */
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0);
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0);
-
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX,
-			    IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
-			    IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
-			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));
-
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX,
-			    IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
-			    IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
-			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));
-#endif
-
 #if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart3), okay) && CONFIG_SERIAL
 	/* LPUART3 TX/RX */
 	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0);
@@ -400,20 +384,6 @@ static int mimxrt1060_evk_init(const struct device *dev)
 			    IOMUXC_SW_PAD_CTL_PAD_DSE(6));
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(sai1), okay) && CONFIG_I2S
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 1U);
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 1U);
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 1U);
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 1U);
-	IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 1U);
-
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 0x10B0u);
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 0x10B0u);
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 0x10B0u);
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 0x10B0u);
-	IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 0x10B0u);
-#endif
-
 	return 0;
 }
 

drivers/i2s/i2s_mcux_sai.c

@@ -16,8 +16,10 @@
 #include <device.h>
 #include <init.h>
 #include <drivers/dma.h>
-
 #include <drivers/i2s.h>
+#ifdef CONFIG_PINCTRL
+#include <drivers/pinctrl.h>
+#endif
 #include <drivers/clock_control.h>
 #include <dt-bindings/clock/imx_ccm.h>
 #include <soc.h>
@@ -78,6 +80,9 @@ struct i2s_mcux_config {
 	uint32_t tx_channel;
 	clock_control_subsys_t clk_sub_sys;
 	const struct device *ccm_dev;
+#ifdef CONFIG_PINCTRL
+	const struct pinctrl_dev_config *pinctrl;
+#endif
 	void (*irq_connect)(const struct device *dev);
 	bool rx_sync_mode;
 	bool tx_sync_mode;
@@ -335,7 +340,6 @@ static void enable_mclk_direction(const struct device *dev, bool dir)
 	} else {
 		*gpr &= ~mask;
 	}
-
 }
 
 static void get_mclk_rate(const struct device *dev, uint32_t *mclk)
@@ -969,6 +973,9 @@ static int i2s_mcux_initialize(const struct device *dev)
 	I2S_Type *base = (I2S_Type *)dev_cfg->base;
 	struct i2s_dev_data *dev_data = dev->data;
 	uint32_t mclk;
+#ifdef CONFIG_PINCTRL
+	int err;
+#endif
 
 	if (!dev_data->dev_dma) {
 		LOG_ERR("DMA device not found");
@@ -987,6 +994,14 @@ static int i2s_mcux_initialize(const struct device *dev)
 
 	/* register ISR */
 	dev_cfg->irq_connect(dev);
+	/* pinctrl */
+#ifdef CONFIG_PINCTRL
+	err = pinctrl_apply_state(dev_cfg->pinctrl, PINCTRL_STATE_DEFAULT);
+	if (err) {
+		LOG_ERR("mclk pinctrl setup failed (%d)", err);
+		return err;
+	}
+#endif
 
 	/*clock configuration*/
 	audio_clock_settings(dev);
@@ -1036,9 +1051,19 @@ static const struct i2s_driver_api i2s_mcux_driver_api = {
 	.trigger = i2s_mcux_trigger,
 };
 
+#ifdef CONFIG_PINCTRL
+#define PINCTRL_DEFINE(i2s_id) PINCTRL_DT_INST_DEFINE(i2s_id);
+#define PINCTRL_INIT(i2s_id) .pinctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(i2s_id),
+#else
+#define PINCTRL_DEFINE(i2s_id)
+#define PINCTRL_INIT(i2s_id)
+#endif
+
 #define I2S_MCUX_INIT(i2s_id)						\
 	static void i2s_irq_connect_##i2s_id(const struct device *dev); \
 									\
+	PINCTRL_DEFINE(i2s_id)						\
+									\
 	static const struct i2s_mcux_config i2s_##i2s_id##_config = {	\
 		.base = (I2S_Type *)DT_INST_REG_ADDR(i2s_id),		\
 		.clk_src =						\
@@ -1071,6 +1096,7 @@ static const struct i2s_driver_api i2s_mcux_driver_api = {
 			DT_INST_CLOCKS_CELL_BY_IDX(i2s_id, 0, name),	\
 		.ccm_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(i2s_id)),	\
 		.irq_connect = i2s_irq_connect_##i2s_id,		\
+		PINCTRL_INIT(i2s_id)					\
 		.tx_sync_mode =						\
 			   DT_INST_PROP(i2s_id, nxp_tx_sync_mode),	\
 		.rx_sync_mode =						\

drivers/pinctrl/CMakeLists.txt

@@ -12,3 +12,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_RPI_PICO pinctrl_rpi_pico.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_STM32 pinctrl_stm32.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_KINETIS pinctrl_kinetis.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCUX_RT pinctrl_mcux_rt.c)

drivers/pinctrl/Kconfig

@@ -37,5 +37,6 @@ source "drivers/pinctrl/Kconfig.rpi_pico"
 source "drivers/pinctrl/Kconfig.stm32"
 source "drivers/pinctrl/Kconfig.kinetis"
 source "drivers/pinctrl/Kconfig.xec"
+source "drivers/pinctrl/Kconfig.mcux"
 
 endif # PINCTRL

drivers/pinctrl/Kconfig.mcux

@@ -0,0 +1,11 @@
+# Copyright (c) 2022 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+DT_COMPAT_MCUX_RT_PINCTRL := nxp,mcux-rt-pinctrl
+
+config PINCTRL_MCUX_RT
+	bool "Pin controller driver for MCUX RT1xxx MCUs"
+	depends on SOC_SERIES_IMX_RT
+	default $(dt_compat_enabled,$(DT_COMPAT_MCUX_RT_PINCTRL))
+	help
+	  Enable pin controller driver for NXP RT series MCUs

drivers/pinctrl/pinctrl_mcux_rt.c

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2022 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_mcux_rt_pinctrl
+
+#include <drivers/pinctrl.h>
+#include <soc.h>
+#include <fsl_iomuxc.h>
+#include <fsl_gpio.h>
+
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
+			   uintptr_t reg)
+{
+	/* configure all pins */
+	for (uint8_t i = 0U; i < pin_cnt; i++) {
+		uint32_t mux_register = pins[i].pinmux.mux_register;
+		uint32_t mux_mode = pins[i].pinmux.mux_mode;
+		uint32_t input_register = pins[i].pinmux.input_register;
+		uint32_t input_daisy = pins[i].pinmux.input_daisy;
+		uint32_t config_register = pins[i].pinmux.config_register;
+		uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags;
+
+		IOMUXC_SetPinMux(mux_register, mux_mode, input_register,
+			input_daisy, config_register,
+			MCUX_RT_INPUT_ENABLE(pin_ctrl_flags));
+
+		IOMUXC_SetPinConfig(mux_register, mux_mode, input_register,
+			input_daisy, config_register,
+			pin_ctrl_flags & (~(0x1 << MCUX_RT_INPUT_ENABLE_SHIFT)));
+	}
+	return 0;
+}
+
+static int mcux_pinctrl_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	CLOCK_EnableClock(kCLOCK_Iomuxc);
+	CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
+
+	return 0;
+}
+
+SYS_INIT(mcux_pinctrl_init, PRE_KERNEL_1, 0);