Atmel SAM: Introduce SMC driver

boards/arm/sam4s_xplained/doc/index.rst

@@ -55,6 +55,8 @@ features:
 +-----------+------------+-------------------------------------+
 | HWINFO    | on-chip    | Unique device serial number         |
 +-----------+------------+-------------------------------------+
+| SMC       | on-chip    | memc (PSRAM)                        |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not currently supported by Zephyr.
 

boards/arm/sam4s_xplained/sam4s_xplained-pinctrl.dtsi

@@ -41,4 +41,39 @@
 				 <PA22A_USART1_TXD>;
 		};
 	};
+	smc_default: smc_default {
+		group1 {
+			pinmux = <PC18A_EBI_A0>,
+				 <PC19A_EBI_A1>,
+				 <PC20A_EBI_A2>,
+				 <PC21A_EBI_A3>,
+				 <PC22A_EBI_A4>,
+				 <PC23A_EBI_A5>,
+				 <PC24A_EBI_A6>,
+				 <PC25A_EBI_A7>,
+				 <PC26A_EBI_A8>,
+				 <PC27A_EBI_A9>,
+				 <PC28A_EBI_A10>,
+				 <PC29A_EBI_A11>,
+				 <PC30A_EBI_A12>,
+				 <PC31A_EBI_A13>,
+				 <PA18C_EBI_A14>,
+				 <PA19C_EBI_A15>,
+				 <PA20C_EBI_A16>,
+				 <PA0C_EBI_A17>,
+				 <PA1C_EBI_A18>,
+				 <PC0A_EBI_D0>,
+				 <PC1A_EBI_D1>,
+				 <PC2A_EBI_D2>,
+				 <PC3A_EBI_D3>,
+				 <PC4A_EBI_D4>,
+				 <PC5A_EBI_D5>,
+				 <PC6A_EBI_D6>,
+				 <PC7A_EBI_D7>,
+				 <PC14A_EBI_NCS0>,
+				 <PC15A_EBI_NCS1>,
+				 <PC11A_EBI_NRD>,
+				 <PC8A_EBI_NWE>;
+		};
+	};
 };

boards/arm/sam4s_xplained/sam4s_xplained.dts

@@ -28,6 +28,20 @@
 		zephyr,flash = &flash0;
 	};
 
+	sram1: sram@60000000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		device_type = "memory";
+		reg = <0x60000000 DT_SIZE_K(512)>;
+		zephyr,memory-region = "SRAM1";
+	};
+
+	sram2: sram@61000000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		device_type = "memory";
+		reg = <0x61000000 DT_SIZE_K(512)>;
+		zephyr,memory-region = "SRAM2";
+	};
+
 	leds {
 		compatible = "gpio-leds";
 		yellow_led_1: led_1 {
@@ -175,3 +189,29 @@ xplained4_spi: &spi0 {
 
 xplained4_serial: &uart1 {
 };
+
+&smc {
+	status = "okay";
+	pinctrl-0 = <&smc_default>;
+	pinctrl-names = "default";
+
+	is66wv51216dbll@0 {
+		reg = <0>;
+
+		atmel,smc-write-mode = "nwe";
+		atmel,smc-read-mode = "nrd";
+		atmel,smc-setup-timing = <1 1 1 1>;
+		atmel,smc-pulse-timing = <6 6 6 6>;
+		atmel,smc-cycle-timing = <7 7>;
+	};
+
+	is66wv51216dbll@1 {
+		reg = <1>;
+
+		atmel,smc-write-mode = "nwe";
+		atmel,smc-read-mode = "nrd";
+		atmel,smc-setup-timing = <1 1 1 1>;
+		atmel,smc-pulse-timing = <6 6 6 6>;
+		atmel,smc-cycle-timing = <7 7>;
+	};
+};

boards/arm/sam4s_xplained/sam4s_xplained.yaml

@@ -8,6 +8,7 @@ toolchain:
   - xtools
 supported:
   - gpio
+  - memc
   - spi
   - watchdog
   - xplained_gpio

boards/arm/sam4s_xplained/sam4s_xplained_defconfig

@@ -12,5 +12,8 @@ CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK=y
 CONFIG_GPIO=y
 CONFIG_WDT_DISABLE_AT_BOOT=y
 
+# Enable SMC SRAM
+CONFIG_MEMC=y
+
 # Enable HW stack protection
 CONFIG_HW_STACK_PROTECTION=y

drivers/memc/CMakeLists.txt

@@ -10,6 +10,8 @@ zephyr_library_sources_ifdef(CONFIG_MEMC_STM32_NOR_PSRAM memc_stm32_nor_psram.c)
 zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI memc_mcux_flexspi.c)
 zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_HYPERRAM memc_mcux_flexspi_hyperram.c)
 
+zephyr_library_sources_ifdef(CONFIG_MEMC_SAM_SMC memc_sam_smc.c)
+
 if(CONFIG_FLASH_MCUX_FLEXSPI_XIP)
   zephyr_code_relocate(memc_mcux_flexspi.c ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT)
 endif()

drivers/memc/Kconfig

@@ -25,4 +25,6 @@ source "drivers/memc/Kconfig.stm32"
 
 source "drivers/memc/Kconfig.mcux"
 
+source "drivers/memc/Kconfig.sam"
+
 endif

drivers/memc/Kconfig.sam

@@ -0,0 +1,9 @@
+# Copyright (c) 2022 Basalte bv
+# SPDX-License-Identifier: Apache-2.0
+
+config MEMC_SAM_SMC
+	bool "Atmel Static Memory Controller (SMC)"
+	default y
+	depends on DT_HAS_ATMEL_SAM_SMC_ENABLED
+	help
+	  Enable Atmel Static Memory Controller.

drivers/memc/memc_sam_smc.c

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2022 Basalte bv
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT atmel_sam_smc
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <soc.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(memc_sam, CONFIG_MEMC_LOG_LEVEL);
+
+struct memc_smc_bank_config {
+	uint32_t cs;
+	uint32_t mode;
+	uint32_t setup_timing;
+	uint32_t pulse_timing;
+	uint32_t cycle_timing;
+};
+
+struct memc_smc_config {
+	Smc *regs;
+	uint32_t periph_id;
+
+	size_t banks_len;
+	const struct memc_smc_bank_config *banks;
+
+	const struct pinctrl_dev_config *pcfg;
+};
+
+static int memc_smc_init(const struct device *dev)
+{
+	int ret;
+	const struct memc_smc_config *cfg = dev->config;
+	SmcCs_number *bank;
+
+	soc_pmc_peripheral_enable(cfg->periph_id);
+
+	ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		return ret;
+	}
+
+	for (size_t i = 0U; i < cfg->banks_len; i++) {
+		if (cfg->banks[i].cs >= SMCCS_NUMBER_NUMBER) {
+			return -EINVAL;
+		}
+
+		bank = &cfg->regs->SMC_CS_NUMBER[cfg->banks[i].cs];
+
+		bank->SMC_SETUP = cfg->banks[i].setup_timing;
+		bank->SMC_PULSE = cfg->banks[i].pulse_timing;
+		bank->SMC_CYCLE = cfg->banks[i].cycle_timing;
+		bank->SMC_MODE = cfg->banks[i].mode;
+	}
+
+	return 0;
+}
+
+#define SETUP_TIMING(node_id)								\
+	SMC_SETUP_NWE_SETUP(DT_PROP_BY_IDX(node_id, atmel_smc_setup_timing, 0))		\
+	| SMC_SETUP_NCS_WR_SETUP(DT_PROP_BY_IDX(node_id, atmel_smc_setup_timing, 1))	\
+	| SMC_SETUP_NRD_SETUP(DT_PROP_BY_IDX(node_id, atmel_smc_setup_timing, 2))	\
+	| SMC_SETUP_NCS_RD_SETUP(DT_PROP_BY_IDX(node_id, atmel_smc_setup_timing, 3))
+#define PULSE_TIMING(node_id)								\
+	SMC_PULSE_NWE_PULSE(DT_PROP_BY_IDX(node_id, atmel_smc_pulse_timing, 0))		\
+	| SMC_PULSE_NCS_WR_PULSE(DT_PROP_BY_IDX(node_id, atmel_smc_pulse_timing, 1))	\
+	| SMC_PULSE_NRD_PULSE(DT_PROP_BY_IDX(node_id, atmel_smc_pulse_timing, 2))	\
+	| SMC_PULSE_NCS_RD_PULSE(DT_PROP_BY_IDX(node_id, atmel_smc_pulse_timing, 3))
+#define CYCLE_TIMING(node_id)								\
+	SMC_CYCLE_NWE_CYCLE(DT_PROP_BY_IDX(node_id, atmel_smc_cycle_timing, 0))		\
+	| SMC_CYCLE_NRD_CYCLE(DT_PROP_BY_IDX(node_id, atmel_smc_cycle_timing, 1))
+
+#define BANK_CONFIG(node_id)								\
+	{										\
+		.cs = DT_REG_ADDR(node_id),						\
+		.mode = COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_write_mode),		\
+				    (SMC_MODE_WRITE_MODE), (0))				\
+			| COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_read_mode),	\
+				      (SMC_MODE_READ_MODE), (0)),			\
+		.setup_timing = SETUP_TIMING(node_id),					\
+		.pulse_timing = PULSE_TIMING(node_id),					\
+		.cycle_timing = CYCLE_TIMING(node_id),					\
+	},
+
+#define MEMC_SMC_DEFINE(inst)								\
+	static const struct memc_smc_bank_config smc_bank_config_##inst[] = {		\
+		DT_INST_FOREACH_CHILD(inst, BANK_CONFIG)				\
+	};										\
+	PINCTRL_DT_INST_DEFINE(inst);							\
+	static const struct memc_smc_config smc_config_##inst = {			\
+		.regs = (Smc *)DT_INST_REG_ADDR(inst),					\
+		.periph_id = DT_INST_PROP(inst, peripheral_id),				\
+		.banks_len = ARRAY_SIZE(smc_bank_config_##inst),			\
+		.banks = smc_bank_config_##inst,					\
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),				\
+	};										\
+	DEVICE_DT_INST_DEFINE(inst, memc_smc_init, NULL, NULL,				\
+			      &smc_config_##inst, POST_KERNEL,				\
+			      CONFIG_MEMC_INIT_PRIORITY, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(MEMC_SMC_DEFINE)

dts/arm/atmel/sam4e.dtsi

@@ -232,6 +232,15 @@
 			peripheral-id = <27 28 29>;
 			status = "disabled";
 		};
+
+		smc: smc@40060000 {
+			compatible = "atmel,sam-smc";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40060000 0x200>;
+			peripheral-id = <8>;
+			status = "disabled";
+		};
 	};
 };
 

dts/arm/atmel/sam4s.dtsi

@@ -194,6 +194,15 @@
 			peripheral-id = <1>;
 			user-nrst;
 		};
+
+		smc: smc@400e0000 {
+			compatible = "atmel,sam-smc";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x400e0000 0x200>;
+			peripheral-id = <10>;
+			status = "disabled";
+		};
 	};
 };
 

dts/arm/atmel/sam4sa16c.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2022 Basalte bv
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/sam4s.dtsi>
+
+/ {
+	soc {
+		flash-controller@400e0a00 {
+			flash0: flash@400000 {
+				reg = <0x00400000 DT_SIZE_K(1024)>;
+			};
+		};
+
+		sram0: memory@20100000 {
+			reg = <0x20100000 DT_SIZE_K(160)>;
+		};
+	};
+};