soc: arm: stm32h7: expand linker with sram sections 1 to 3 #56159
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In zephyrproject-rtos#53184 a linker section for SRAM4 was added because it's required for use with the STM32H7 BDMA. Now in zephyrproject-rtos#52965 support was added for the ADC DMA which expects a similar linker section which is non-cachable, but is limited to use SRAM4 to place it's buffers. This commit gives the user more flexibility to use any SRAM region to place buffers to use with ADC DMA. The region SRAM0 isn't supported because it doesn't have the "zephyr,memory-region" compatibility required to turn it into a non-cacheable region, meaning it doesn't fit the mentioned use case. Signed-off-by: Hein Wessels <[email protected]>
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Closing this, as this is not the correct way to define linker sections. It's already generated automatically for regions in the DTS with the |
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@heinwessels I wonder about the difference between this and the use of dt prop |
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:-D |
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I rather created a PR to remove generating a linker section manually in #56177 |
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In #53184 a linker section for SRAM4 was added because it's required for use with the STM32H7 BDMA. Now in #52965 support was added for the ADC DMA which expects a similar linker section which is non-cachable, but is limited to use SRAM4 to place it's buffers. This commit gives the user more flexibility to use any SRAM region to place buffers to use with ADC DMA.
The region SRAM0 isn't supported because it doesn't have the "zephyr,memory-region" compatibility required to turn it into a non-cacheable region, meaning it doesn't fit the mentioned use case.