zephyrproject-rtos · carlescufi · Jul 25, 2023 · Jul 5, 2023 · Jul 5, 2023 · Jul 7, 2023
diff --git a/boards/arm/arduino_giga_r1/arduino_giga_r1_m7.dts b/boards/arm/arduino_giga_r1/arduino_giga_r1_m7.dts
@@ -29,7 +29,7 @@
 		device_type = "memory";
 		reg = <0xc0000000 DT_SIZE_M(8)>;
 		zephyr,memory-region = "SDRAM1";
-		zephyr,memory-region-mpu = "RAM";
+		zephyr,memory-attr = "RAM";
 	};
 
 	aliases {

diff --git a/boards/arm/stm32f746g_disco/stm32f746g_disco.dts b/boards/arm/stm32f746g_disco/stm32f746g_disco.dts
@@ -45,7 +45,7 @@
 		device_type = "memory";
 		reg = <0xc0000000 DT_SIZE_M(16)>;
 		zephyr,memory-region = "SDRAM1";
-		zephyr,memory-region-mpu = "RAM";
+		zephyr,memory-attr = "RAM";
 	};
 
 	aliases {

diff --git a/boards/arm/stm32f7508_dk/stm32f7508_dk.dts b/boards/arm/stm32f7508_dk/stm32f7508_dk.dts
@@ -46,7 +46,7 @@
 		device_type = "memory";
 		reg = <0xc0000000 DT_SIZE_M(16)>;
 		zephyr,memory-region = "SDRAM1";
-		zephyr,memory-region-mpu = "RAM";
+		zephyr,memory-attr = "RAM";
 	};
 
 	aliases {

diff --git a/boards/arm/stm32f769i_disco/stm32f769i_disco.dts b/boards/arm/stm32f769i_disco/stm32f769i_disco.dts
@@ -28,7 +28,7 @@
 		device_type = "memory";
 		reg = <0xc0000000 DT_SIZE_M(16)>;
 		zephyr,memory-region = "SDRAM1";
-		zephyr,memory-region-mpu = "RAM";
+		zephyr,memory-attr = "RAM";
 	};
 
 	leds {

diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts b/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts
@@ -27,7 +27,7 @@
 		device_type = "memory";
 		reg = <0xd0000000 DT_SIZE_M(32)>;
 		zephyr,memory-region = "SDRAM2";
-		zephyr,memory-region-mpu = "RAM";
+		zephyr,memory-attr = "RAM";
 	};
 
 	leds {

diff --git a/boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.dts b/boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.dts
@@ -48,7 +48,7 @@
 		device_type = "memory";
 		reg = <0xd0000000 DT_SIZE_M(16)>;
 		zephyr,memory-region = "SDRAM2";
-		zephyr,memory-region-mpu = "RAM";
+		zephyr,memory-attr = "RAM";
 	};
 
 	transceiver0: can-phy0 {

diff --git a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.dts b/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.dts
@@ -41,7 +41,7 @@
 			compatible = "zephyr,memory-region", "mmio-dram";
 			reg = <0x80000000 DT_SIZE_M(2048)>;
 			zephyr,memory-region = "DEVICE_REGION";
-			zephyr,memory-region-mpu = "IO";
+			zephyr,memory-attr = "IO";
 		};
 	};
 };

diff --git a/doc/build/dts/api/api.rst b/doc/build/dts/api/api.rst
@@ -294,6 +294,15 @@ and properties related to them.
 
 .. doxygengroup:: devicetree-mbox
 
+.. _devicetree-memory-attr-api:
+
+Memory attributes
+=================
+
+These conveniences may be used for nodes with a memory attribute property.
+
+.. doxygengroup:: devicetree-memory-attr
+
 .. _devicetree-pinctrl-api:
 
 Pinctrl (pin control)

diff --git a/doc/hardware/arch/arm_cortex_m.rst b/doc/hardware/arch/arm_cortex_m.rst
@@ -440,9 +440,8 @@ are programmed during system boot.
   SRAM. (An exception to this setting is when :kconfig:option:`CONFIG_MPU_GAP_FILLING` is disabled (Arm v8-M only);
   in that case no SRAM MPU programming is done so the access is determined by the default
   Arm memory map policies, allowing for privileged-only RWX permissions on SRAM).
-* All the memory regions defined in the devicetree with the compatible
-  :dtcompatible:`zephyr,memory-region` and at least the property
-  ``zephyr,memory-region-mpu`` defining the MPU permissions for the memory region.
+* All the memory regions defined in the devicetree with the property
+  ``zephyr,memory-attr`` defining the MPU permissions for the memory region.
   See the next section for more details.
 
 The above MPU regions are defined in :file:`soc/arm/common/cortex_m/arm_mpu_regions.c`.
@@ -453,13 +452,12 @@ configure its own fixed MPU regions in the SoC definition.
 Fixed MPU regions defined in devicetree
 ---------------------------------------
 
-The user can define memory regions to be allocated and created in the linker
-script using nodes with the :dtcompatible:`zephyr,memory-region` devicetree
-compatible. When the property ``zephyr,memory-region-mpu`` is present in such
-a node, a new MPU region will be allocated and programmed during system
-boot.
+When the property ``zephyr,memory-attr`` is present in a memory node, a new MPU
+region will be allocated and programmed during system boot. When used with the
+:dtcompatible:`zephyr,memory-region` devicetree compatible, it will result in a
+linker section being generated associated to that MPU region.
 
-The property ``zephyr,memory-region-mpu`` is a string carrying the attributes
+The property ``zephyr,memory-attr`` is a string carrying the attributes
 for the MPU region. It is converted to a C token for use defining the attributes
 of the MPU region.
 
@@ -471,7 +469,7 @@ For example, to define a new non-cacheable memory region in devicetree:
         compatible = "zephyr,memory-region", "mmio-sram";
         reg = <0x20300000 0x100000>;
         zephyr,memory-region = "SRAM_NO_CACHE";
-        zephyr,memory-region-mpu = "RAM_NOCACHE";
+        zephyr,memory-attr = "RAM_NOCACHE";
    };
 
 This will automatically create a new MPU entry in

diff --git a/doc/releases/release-notes-3.5.rst b/doc/releases/release-notes-3.5.rst
@@ -237,6 +237,14 @@ USB
 Devicetree
 **********
 
+* ``zephyr,memory-region-mpu`` was renamed ``zephyr,memory-attr``
+
+* The following macros were added:
+  :c:macro:`DT_FOREACH_NODE_VARGS`,
+  :c:macro:`DT_FOREACH_STATUS_OKAY_NODE_VARGS`
+  :c:macro:`DT_MEMORY_ATTR_FOREACH_NODE`
+  :c:macro:`DT_MEMORY_ATTR_APPLY`
+
 Libraries / Subsystems
 **********************
 

diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c
@@ -251,20 +251,20 @@ static int adc_stm32_dma_start(const struct device *dev,
  * The entire buffer must be in a single region.
  * An example of how the SRAM region can be defined in the DTS:
  *	&sram4 {
- *		zephyr,memory-region-mpu = "RAM_NOCACHE";
+ *		zephyr,memory-attr = "RAM_NOCACHE";
  *	};
  */
 static bool address_in_non_cacheable_sram(const uint16_t *buffer, const uint16_t size)
 {
 	/* Default if no valid SRAM region found or buffer+size not located in a single region */
 	bool cachable = false;
 #define IS_NON_CACHEABLE_REGION_FN(node_id)                                                    \
-	COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_region_mpu), ({                    \
+	COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_attr), ({                          \
 			const uint32_t region_start = DT_REG_ADDR(node_id);                    \
 			const uint32_t region_end = region_start + DT_REG_SIZE(node_id);       \
 			if (((uint32_t)buffer >= region_start) &&                              \
 				(((uint32_t)buffer + size) < region_end)) {                    \
-				cachable = strcmp(DT_PROP(node_id, zephyr_memory_region_mpu),  \
+				cachable = strcmp(DT_PROP(node_id, zephyr_memory_attr),        \
 						"RAM_NOCACHE") == 0;                           \
 			}                                                                      \
 		}),                                                                            \

diff --git a/drivers/dma/dma_stm32_bdma.c b/drivers/dma/dma_stm32_bdma.c
@@ -809,11 +809,11 @@ static int bdma_stm32_init(const struct device *dev)
 	 * This check verifies that the non-cachable flag is set in the DTS.
 	 * For example:
 	 *	&sram4 {
-	 *		zephyr,memory-region-mpu = "RAM_NOCACHE";
+	 *		zephyr,memory-attr = "RAM_NOCACHE";
 	 *	};
 	 */
-#if DT_NODE_HAS_PROP(DT_NODELABEL(sram4), zephyr_memory_region_mpu)
-	if (strcmp(DT_PROP(DT_NODELABEL(sram4), zephyr_memory_region_mpu), "RAM_NOCACHE") != 0) {
+#if DT_NODE_HAS_PROP(DT_NODELABEL(sram4), zephyr_memory_attr)
+	if (strcmp(DT_PROP(DT_NODELABEL(sram4), zephyr_memory_attr), "RAM_NOCACHE") != 0) {
 		LOG_ERR("SRAM4 is not set as non-cachable.");
 		return -EIO;
 	}

diff --git a/dts/arm/nxp/nxp_lpc55S1x_common.dtsi b/dts/arm/nxp/nxp_lpc55S1x_common.dtsi
@@ -61,7 +61,7 @@
 		compatible = "zephyr,memory-region", "mmio-sram";
 		reg = <0x20010000 DT_SIZE_K(16)>;
 		zephyr,memory-region = "USB_SRAM";
-		zephyr,memory-region-mpu = "RAM";
+		zephyr,memory-attr = "RAM";
 	};
 };
 

diff --git a/dts/arm/nxp/nxp_lpc55S2x_common.dtsi b/dts/arm/nxp/nxp_lpc55S2x_common.dtsi
@@ -75,7 +75,7 @@
 		compatible = "zephyr,memory-region", "mmio-sram";
 		reg = <0x40100000  DT_SIZE_K(16)>;
 		zephyr,memory-region = "USB_SRAM";
-		zephyr,memory-region-mpu = "RAM";
+		zephyr,memory-attr = "RAM";
 	};
 };
 

diff --git a/dts/arm/nxp/nxp_lpc55S6x_common.dtsi b/dts/arm/nxp/nxp_lpc55S6x_common.dtsi
@@ -95,7 +95,7 @@
 		compatible = "zephyr,memory-region", "mmio-sram";
 		reg = <0x100000 DT_SIZE_K(16)>;
 		zephyr,memory-region = "USB_SRAM";
-		zephyr,memory-region-mpu = "RAM";
+		zephyr,memory-attr = "RAM";
 	};
 
 	syscon: syscon@0 {

diff --git a/dts/arm/nxp/nxp_rt5xx_common.dtsi b/dts/arm/nxp/nxp_rt5xx_common.dtsi
@@ -49,7 +49,7 @@
 		compatible =  "zephyr,memory-region", "mmio-sram";
 		reg = <0x40140000 DT_SIZE_K(16)>;
 		zephyr,memory-region = "SRAM1";
-		zephyr,memory-region-mpu = "RAM";
+		zephyr,memory-attr = "RAM";
 	};
 };
 

diff --git a/dts/arm/nxp/nxp_rt6xx_common.dtsi b/dts/arm/nxp/nxp_rt6xx_common.dtsi
@@ -48,7 +48,7 @@
 		compatible =  "zephyr,memory-region", "mmio-sram";
 		reg = <0x40140000 DT_SIZE_K(16)>;
 		zephyr,memory-region = "SRAM1";
-		zephyr,memory-region-mpu = "RAM";
+		zephyr,memory-attr = "RAM";
 	};
 };
 

diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi
@@ -47,7 +47,7 @@
 		compatible = "zephyr,memory-region", "mmio-sram";
 		reg = <0x90000000 DT_SIZE_M(256)>;
 		zephyr,memory-region = "QSPI";
-		zephyr,memory-region-mpu = "EXTMEM";
+		zephyr,memory-attr = "EXTMEM";
 	};
 
 	clocks {

diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi
@@ -48,7 +48,7 @@
 		compatible = "zephyr,memory-region", "mmio-sram";
 		reg = <0x90000000 DT_SIZE_M(256)>;
 		zephyr,memory-region = "QSPI";
-		zephyr,memory-region-mpu = "EXTMEM";
+		zephyr,memory-attr = "EXTMEM";
 	};
 
 	clocks {

diff --git a/dts/bindings/base/zephyr,memory-attr.yaml b/dts/bindings/base/zephyr,memory-attr.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2023, Carlo Caione <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+include: [base.yaml]
+
+properties:
+  zephyr,memory-attr:
+    type: string
+    enum:
+      - "RAM"
+      - "RAM_NOCACHE"
+      - "FLASH"
+      - "PPB"
+      - "IO"
+      - "EXTMEM"
+    description: |
+      Attribute for the memory region.
+
+  reg:
+    required: true
diff --git a/dts/bindings/base/zephyr,memory-region.yaml b/dts/bindings/base/zephyr,memory-region.yaml
@@ -5,7 +5,7 @@ description: Compatible for devices resulting in linker memory regions
 
 compatible: "zephyr,memory-region"
 
-include: base.yaml
+include: [base.yaml, "zephyr,memory-attr.yaml"]
 
 properties:
   zephyr,memory-region:
@@ -16,17 +16,3 @@ properties:
       memory region in the final executable. The region address and size
       is taken from the <reg> property, while the name is the value of
       this property.
-
-  zephyr,memory-region-mpu:
-    type: string
-    enum:
-      - "RAM"
-      - "RAM_NOCACHE"
-      - "FLASH"
-      - "PPB"
-      - "IO"
-      - "EXTMEM"
-    description: |
-      Signify that this node should result in a dedicated MPU region. The
-      region address and size are taken from the <reg> property, while the MPU
-      attribute is the value of this property.
diff --git a/dts/bindings/test/vnd,memory-attr.yaml b/dts/bindings/test/vnd,memory-attr.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2020 Linaro Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Test memory and memory attributes
+
+compatible: "vnd,memory-attr"
+
+include: [base.yaml, "zephyr,memory-attr.yaml"]
diff --git a/include/zephyr/devicetree.h b/include/zephyr/devicetree.h
@@ -4286,5 +4286,6 @@
 #include <zephyr/devicetree/can.h>
 #include <zephyr/devicetree/reset.h>
 #include <zephyr/devicetree/mbox.h>
+#include <zephyr/devicetree/memory-attr.h>
 
 #endif /* DEVICETREE_H */