Add support for SOPHGO SoCs and Milk-V boards #69594
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| /* | ||
| * Copyright (c) 2024 Chen Xingyu <[email protected]> | ||
| * SPDX-License-Identifier: Apache-2.0 | ||
| */ | ||
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| #include <mem.h> | ||
| #include <freq.h> | ||
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| #include <sophgo/cv18xx-c906-common.dtsi> | ||
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| / { | ||
| soc { | ||
| compatible = "sophgo,cv181x", "simple-bus"; | ||
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| gpioa: gpio@3020000 { | ||
| compatible = "snps,designware-gpio"; | ||
| reg = <0x3020000 DT_SIZE_K(4)>; | ||
| interrupts = <41 1>; | ||
| gpio-controller; | ||
| #gpio-cells = <2>; | ||
| status = "disabled"; | ||
| }; | ||
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| gpiob: gpio@3021000 { | ||
| compatible = "snps,designware-gpio"; | ||
| reg = <0x3021000 DT_SIZE_K(4)>; | ||
| interrupts = <42 1>; | ||
| gpio-controller; | ||
| #gpio-cells = <2>; | ||
| status = "disabled"; | ||
| }; | ||
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| gpioc: gpio@3022000 { | ||
| compatible = "snps,designware-gpio"; | ||
| reg = <0x3022000 DT_SIZE_K(4)>; | ||
| interrupts = <43 1>; | ||
| gpio-controller; | ||
| #gpio-cells = <2>; | ||
| status = "disabled"; | ||
| }; | ||
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| gpiod: gpio@3023000 { | ||
| compatible = "snps,designware-gpio"; | ||
| reg = <0x3023000 DT_SIZE_K(4)>; | ||
| interrupts = <44 1>; | ||
| gpio-controller; | ||
| #gpio-cells = <2>; | ||
| status = "disabled"; | ||
| }; | ||
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| uart0: uart@4140000 { | ||
| compatible = "ns16550"; | ||
| reg = <0x4140000 DT_SIZE_K(64)>; | ||
| interrupts = <30 1>; | ||
| reg-shift = <2>; | ||
| clock-frequency = <DT_FREQ_M(25)>; | ||
| status = "disabled"; | ||
| }; | ||
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| uart1: uart@4150000 { | ||
| compatible = "ns16550"; | ||
| reg = <0x4150000 DT_SIZE_K(64)>; | ||
| interrupts = <31 1>; | ||
| reg-shift = <2>; | ||
| clock-frequency = <DT_FREQ_M(25)>; | ||
| status = "disabled"; | ||
| }; | ||
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| uart2: uart@4160000 { | ||
| compatible = "ns16550"; | ||
| reg = <0x4160000 DT_SIZE_K(64)>; | ||
| /* interrupt is not supported */ | ||
| reg-shift = <2>; | ||
| clock-frequency = <DT_FREQ_M(25)>; | ||
| status = "disabled"; | ||
| }; | ||
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| uart3: uart@4170000 { | ||
| compatible = "ns16550"; | ||
| reg = <0x4170000 DT_SIZE_K(64)>; | ||
| /* interrupt is not supported */ | ||
| reg-shift = <2>; | ||
| clock-frequency = <DT_FREQ_M(25)>; | ||
| status = "disabled"; | ||
| }; | ||
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| uart4: uart@41c0000 { | ||
| compatible = "ns16550"; | ||
| reg = <0x41c0000 DT_SIZE_K(64)>; | ||
| /* interrupt is not supported */ | ||
| reg-shift = <2>; | ||
| clock-frequency = <DT_FREQ_M(25)>; | ||
| status = "disabled"; | ||
| }; | ||
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| pwr_gpio: gpio@5021000 { | ||
| compatible = "snps,designware-gpio"; | ||
| reg = <0x5021000 DT_SIZE_K(4)>; | ||
| interrupts = <48 1>; | ||
| gpio-controller; | ||
| #gpio-cells = <2>; | ||
| status = "disabled"; | ||
| }; | ||
| }; | ||
| }; |
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| # SPDX-License-Identifier: Apache-2.0 | ||
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| set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") |
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| # Copyright (c) 2024 Chen Xingyu <[email protected]> | ||
| # SPDX-License-Identifier: Apache-2.0 | ||
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| config SOC_SERIES_CV181X | ||
| select 64BIT | ||
| select RISCV | ||
| select RISCV_PRIVILEGED | ||
| select RISCV_ISA_RV64I | ||
| select RISCV_ISA_EXT_M | ||
| select RISCV_ISA_EXT_A | ||
| select RISCV_ISA_EXT_F | ||
| select RISCV_ISA_EXT_D | ||
| select RISCV_ISA_EXT_C | ||
| select RISCV_ISA_EXT_ZICSR | ||
| select RISCV_ISA_EXT_ZIFENCEI | ||
| select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING | ||
| select INCLUDE_RESET_VECTOR | ||
| select ATOMIC_OPERATIONS_C |
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| # Copyright (c) 2024 Chen Xingyu <[email protected]> | ||
| # SPDX-License-Identifier: Apache-2.0 | ||
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| if SOC_SERIES_CV181X | ||
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| config SYS_CLOCK_HW_CYCLES_PER_SEC | ||
| default 25000000 | ||
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| config NUM_IRQS | ||
| int | ||
| default 128 | ||
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There was a problem hiding this comment. the comment here refers to a point above about removing There was a problem hiding this comment. you need to be very specific, above here, at least for me is the DTS comment above. There was a problem hiding this comment. it's above that, and shows the same thing as this #69594 (comment) |
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| config RISCV_SOC_INTERRUPT_INIT | ||
| default y | ||
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| config RISCV_HAS_PLIC | ||
| default y | ||
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| config 2ND_LVL_INTR_00_OFFSET | ||
| default 11 | ||
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| endif # SOC_SERIES_CV181X | ||
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| # Copyright (c) 2024 Chen Xingyu <[email protected]> | ||
| # SPDX-License-Identifier: Apache-2.0 | ||
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| config SOC_SERIES_CV181X | ||
| bool | ||
| select SOC_FAMILY_SOPHGO | ||
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| config SOC_SERIES | ||
| default "cv181x" if SOC_SERIES_CV181X | ||
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| config SOC_SG2000 | ||
| bool | ||
| select SOC_SERIES_CV181X | ||
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| config SOC_SG2002 | ||
| bool | ||
| select SOC_SERIES_CV181X | ||
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| config SOC | ||
| default "sg2000" if SOC_SG2000 | ||
| default "sg2002" if SOC_SG2002 |
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as above