Add Zephyr RTOS support for WCH CH32V003

MAINTAINERS.yml

@@ -4881,6 +4881,14 @@ West:
   labels:
     - "platform: TI"
 
+"West project: hal_wch":
+  status: maintained
+  maintainers:
+    - nzmichaelh
+    - kholia
+  files:
+    - modules/hal_wch/
+
 "West project: hal_wurthelektronik":
   status: maintained
   maintainers:

boards/common/minichlink.board.cmake

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Dhiru Kholia
+# SPDX-License-Identifier: Apache-2.0
+
+board_set_flasher_ifnset(minichlink)
+board_finalize_runner_args(minichlink)

boards/wch/ch32v003evt/Kconfig.ch32v003evt

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_CH32V003EVT
+	select SOC_CH32V003

boards/wch/ch32v003evt/board.cmake

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt")
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+
+board_runner_args(minichlink)
+include(${ZEPHYR_BASE}/boards/common/minichlink.board.cmake)

boards/wch/ch32v003evt/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: ch32v003evt
+  full_name: WCH CH32V003EVT
+  vendor: wch
+  socs:
+    - name: ch32v003

boards/wch/ch32v003evt/ch32v003evt-pinctrl.dtsi

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024 Michael Hope <[email protected]>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h>
+
+&pinctrl {
+	usart1_default: usart1_default {
+		group1 {
+			pinmux = <USART1_TX_PD5_0>;
+			output-high;
+			drive-push-pull;
+			slew-rate = "max-speed-10mhz";
+		};
+		group2 {
+			pinmux = <USART1_RX_PD6_0>;
+			bias-pull-up;
+		};
+	};
+};

boards/wch/ch32v003evt/ch32v003evt.dts

@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2024 Michael Hope <[email protected]>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <wch/ch32v00x.dtsi>
+#include "ch32v003evt-pinctrl.dtsi"
+
+/ {
+	model = "ch32v003evt";
+	compatible = "wch,ch32v003";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		/*
+		 * Please connect the unconnected LED on the WCH CH32V003EVT
+		 * board to a suitable GPIO pin (like PD4) and then change
+		 * this status to "okay".
+		 */
+		status = "disabled";
+
+		red_led: led0 {
+			gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	aliases {
+		led0 = &red_led;
+	};
+};
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(24)>;
+	status = "okay";
+};
+
+&pll {
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+};
+
+&gpiod {
+	status = "okay";
+};
+
+&usart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&usart1_default>;
+	pinctrl-names = "default";
+};

boards/wch/ch32v003evt/ch32v003evt.yaml

@@ -0,0 +1,11 @@
+identifier: ch32v003evt
+name: WCH CH32V003 Evaluation Board
+type: mcu
+arch: riscv
+toolchain:
+  - cross-compile
+  - zephyr
+ram: 2
+flash: 16
+supported:
+  - gpio

boards/wch/ch32v003evt/ch32v003evt_defconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_GPIO=y
+
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y

boards/wch/ch32v003evt/doc/index.rst

@@ -0,0 +1,107 @@
+.. zephyr:board:: ch32v003evt
+
+Overview
+********
+
+The `WCH`_ CH32V003EVT hardware provides support for QingKe 32-bit RISC-V2A
+processor and the following devices:
+
+* CLOCK
+* :abbr:`GPIO (General Purpose Input Output)`
+* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
+
+The board is equipped with two LEDs. The `WCH webpage on CH32V003`_ contains
+the processor's information and the datasheet.
+
+Hardware
+********
+
+The QingKe 32-bit RISC-V2A processor of the WCH CH32V003EVT is clocked by an
+external crystal and runs at 48 MHz.
+
+Supported Features
+==================
+
+The ``ch32v003evt`` board target supports the following hardware features:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component     |
++===========+============+======================+
+| CLOCK     | on-chip    | clock_control        |
++-----------+------------+----------------------+
+| GPIO      | on-chip    | gpio                 |
++-----------+------------+----------------------+
+| PWM       | on-chip    | pwm                  |
++-----------+------------+----------------------+
+| PINCTRL   | on-chip    | pinctrl              |
++-----------+------------+----------------------+
+| TIMER     | on-chip    | timer                |
++-----------+------------+----------------------+
+| UART      | on-chip    | uart                 |
++-----------+------------+----------------------+
+
+Other hardware features have not been enabled yet for this board.
+
+Connections and IOs
+===================
+
+LED
+---
+
+* LED1 = Unconnected. Connect to an I/O pin (PD4).
+
+Programming and Debugging
+*************************
+
+Applications for the ``ch32v003evt`` board target can be built and flashed
+in the usual way (see :ref:`build_an_application` and :ref:`application_run`
+for more details); however, an external programmer is required since the board
+does not have any built-in debug support.
+
+The following pins of the external programmer must be connected to the
+following pins on the PCB (see image):
+
+* VCC = VCC (do not power the board from the USB port at the same time)
+* GND = GND
+* SWIO = PD1
+
+Flashing
+========
+
+You can use ``minichlink`` to flash the board. Once ``minichlink`` has been set
+up, build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Here is an example for the :zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: ch32v003evt
+   :goals: build flash
+
+Debugging
+=========
+
+This board can be debugged via OpenOCD or ``minichlink``.
+
+Testing the LED on the WCH CH32V003EVT
+**************************************
+
+There is 1 sample program that allow you to test that the LED on the board is
+working properly with Zephyr:
+
+.. code-block:: console
+
+   samples/basic/blinky
+
+You can build and flash the examples to make sure Zephyr is running
+correctly on your board. The button and LED definitions can be found
+in :zephyr_file:`boards/wch/ch32v003evt/ch32v003evt.dts`.
+
+References
+**********
+
+.. target-notes::
+
+.. _WCH: http://www.wch-ic.com
+.. _WCH webpage on CH32V003: https://www.wch-ic.com/products/CH32V003.html

boards/wch/ch32v003evt/support/openocd.cfg

@@ -0,0 +1,15 @@
+#interface wlink
+adapter driver wlink
+wlink_set
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure  -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
+
+echo "Ready for Remote Connections"

boards/wch/index.rst

@@ -0,0 +1,10 @@
+.. _boards-wch:
+
+WCH - Nanjing Qinheng Microelectronics Co.
+##########################################
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*

drivers/clock_control/CMakeLists.txt

@@ -98,3 +98,4 @@ endif()
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AST10X0 clock_control_ast10x0.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MAX32 clock_control_max32.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_AUXPLL clock_control_nrf_auxpll.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_WCH_RCC clock_control_wch_rcc.c)

drivers/clock_control/Kconfig

@@ -100,4 +100,6 @@ source "drivers/clock_control/Kconfig.arm_scmi"
 
 source "drivers/clock_control/Kconfig.silabs"
 
+source "drivers/clock_control/Kconfig.wch_rcc"
+
 endif # CLOCK_CONTROL

drivers/clock_control/Kconfig.wch_rcc

@@ -0,0 +1,7 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+config CLOCK_CONTROL_WCH_RCC
+	bool "WCH CH32V00x Reset and Clock Control (RCC) driver"
+	default y
+	depends on DT_HAS_WCH_RCC_ENABLED