zephyrproject-rtos · carlescufi · Oct 18, 2024 · Sep 17, 2024 · Oct 18, 2024 · Aug 29, 2024
diff --git a/boards/nxp/s32z2xxdc2/doc/index.rst b/boards/nxp/s32z2xxdc2/doc/index.rst
@@ -59,6 +59,8 @@ The boards support the following hardware features:
 +-----------+------------+-------------------------------------+
 | LPI2C     | on-chip    | i2c                                 |
 +-----------+------------+-------------------------------------+
+| EDMA      | on-chip    | dma                                 |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not currently supported by the port.
 
@@ -163,6 +165,12 @@ ADC is provided through ADC SAR controller with 2 instances. Each ADC SAR instan
 .. note::
    All channels of an instance only run on 1 group channel at the same time.
 
+EDMA
+====
+
+The EDMA modules feature four EDMA3 instances: Instance 0 with 32 channels,
+and instances 1, 4, and 5, each with 16 channels.
+
 Programming and Debugging
 *************************
 

diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml
@@ -18,4 +18,5 @@ supported:
   - counter
   - adc
   - i2c
+  - dma
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml
@@ -18,4 +18,5 @@ supported:
   - counter
   - adc
   - i2c
+  - dma
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml
@@ -18,4 +18,5 @@ supported:
   - counter
   - adc
   - i2c
+  - dma
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml
@@ -18,4 +18,5 @@ supported:
   - counter
   - adc
   - i2c
+  - dma
 vendor: nxp
diff --git a/drivers/dma/Kconfig.mcux_edma b/drivers/dma/Kconfig.mcux_edma
@@ -35,10 +35,10 @@ config DMA_TCD_QUEUE_SIZE
 
 config DMA_MCUX_TEST_SLOT_START
 	int "test slot start num"
-	depends on (SOC_SERIES_KINETIS_K6X || SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_S32K3)
+	depends on (SOC_SERIES_KINETIS_K6X || SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_S32K3 || SOC_SERIES_S32ZE)
 	default 58 if SOC_SERIES_KINETIS_K6X
 	default 60 if SOC_SERIES_KINETIS_KE1XF
-	default 62 if SOC_SERIES_S32K3
+	default 62 if SOC_SERIES_S32K3 || SOC_SERIES_S32ZE
 	help
 	  test slot start num
 

diff --git a/drivers/dma/dma_mcux_edma.c b/drivers/dma/dma_mcux_edma.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2020-23 NXP
+ * Copyright 2020-2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -43,11 +43,13 @@ struct dma_mcux_edma_config {
 #endif
 	uint8_t channels_per_mux;
 	uint8_t dmamux_reg_offset;
+	int dma_requests;
 	int dma_channels; /* number of channels */
 #if DMA_MCUX_HAS_CHANNEL_GAP
 	uint32_t channel_gap[2];
 #endif
 	void (*irq_config_func)(const struct device *dev);
+	edma_tcd_t (*tcdpool)[CONFIG_DMA_TCD_QUEUE_SIZE];
 };
 
 
@@ -82,9 +84,6 @@ struct dma_mcux_edma_config {
 
 #endif /* CONFIG_HAS_MCUX_CACHE */
 
-static __aligned(32) EDMA_TCDPOOL_CACHE_ATTR edma_tcd_t
-tcdpool[DT_INST_PROP(0, dma_channels)][CONFIG_DMA_TCD_QUEUE_SIZE];
-
 struct dma_mcux_channel_transfer_edma_settings {
 	uint32_t source_data_size;
 	uint32_t dest_data_size;
@@ -108,8 +107,8 @@ struct call_back {
 
 struct dma_mcux_edma_data {
 	struct dma_context dma_ctx;
-	struct call_back data_cb[DT_INST_PROP(0, dma_channels)];
-	ATOMIC_DEFINE(channels_atomic, DT_INST_PROP(0, dma_channels));
+	struct call_back *data_cb;
+	atomic_t *channels_atomic;
 };
 
 #define DEV_CFG(dev) \
@@ -256,12 +255,12 @@ static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel,
 	unsigned int key;
 	int ret = 0;
 
-	if (slot >= DT_INST_PROP(0, dma_requests)) {
+	if (slot >= DEV_CFG(dev)->dma_requests) {
 		LOG_ERR("source number is out of scope %d", slot);
 		return -ENOTSUP;
 	}
 
-	if (channel >= DT_INST_PROP(0, dma_channels)) {
+	if (channel >= DEV_CFG(dev)->dma_channels) {
 		LOG_ERR("out of DMA channel %d", channel);
 		return -EINVAL;
 	}
@@ -359,7 +358,8 @@ static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel,
 	EDMA_EnableChannelInterrupts(DEV_BASE(dev), hw_channel, kEDMA_ErrorInterruptEnable);
 
 	if (block_config->source_gather_en || block_config->dest_scatter_en) {
-		EDMA_InstallTCDMemory(p_handle, tcdpool[channel], CONFIG_DMA_TCD_QUEUE_SIZE);
+		EDMA_InstallTCDMemory(p_handle, DEV_CFG(dev)->tcdpool[channel],
+				      CONFIG_DMA_TCD_QUEUE_SIZE);
 		while (block_config != NULL) {
 			EDMA_PrepareTransfer(
 				&(data->transferConfig),
@@ -627,8 +627,6 @@ static int dma_mcux_edma_init(const struct device *dev)
 	EDMA_EnableAllChannelLink(DEV_BASE(dev), true);
 #endif
 	config->irq_config_func(dev);
-	memset(dev->data, 0, sizeof(struct dma_mcux_edma_data));
-	memset(tcdpool, 0, sizeof(tcdpool));
 	data->dma_ctx.magic = DMA_MAGIC;
 	data->dma_ctx.dma_channels = config->dma_channels;
 	data->dma_ctx.atomic = data->channels_atomic;
@@ -675,9 +673,9 @@ static int dma_mcux_edma_init(const struct device *dev)
 		LISTIFY(NUM_IRQS_WITHOUT_ERROR_IRQ(n),				\
 			DMA_MCUX_EDMA_IRQ_CONFIG, (;), n)			\
 										\
-		IF_ENABLED(UTIL_NOT(DT_INST_NODE_HAS_PROP(n, no_error_irq)),	\
-			   (IRQ_CONFIG(n, NUM_IRQS_WITHOUT_ERROR_IRQ(n),	\
-			    dma_mcux_edma_error_irq_handler)))			\
+		COND_CODE_1(DT_INST_PROP(n, no_error_irq), (),			\
+			(IRQ_CONFIG(n, NUM_IRQS_WITHOUT_ERROR_IRQ(n),		\
+			dma_mcux_edma_error_irq_handler)))			\
 										\
 		LOG_DBG("install irq done");					\
 	}
@@ -716,17 +714,28 @@ static int dma_mcux_edma_init(const struct device *dev)
 #define DMA_INIT(n)								\
 	DMAMUX_BASE_INIT_DEFINE(n)						\
 	static void dma_imx_config_func_##n(const struct device *dev);		\
+	static __aligned(32) EDMA_TCDPOOL_CACHE_ATTR edma_tcd_t			\
+	dma_tcdpool##n[DT_INST_PROP(n, dma_channels)][CONFIG_DMA_TCD_QUEUE_SIZE];\
 	static const struct dma_mcux_edma_config dma_config_##n = {		\
 		.base = (DMA_Type *)DT_INST_REG_ADDR(n),			\
 		DMAMUX_BASE_INIT(n)						\
+		.dma_requests = DT_INST_PROP(n, dma_requests),			\
 		.dma_channels = DT_INST_PROP(n, dma_channels),			\
 		CHANNELS_PER_MUX(n)						\
 		.irq_config_func = dma_imx_config_func_##n,			\
 		.dmamux_reg_offset = DT_INST_PROP(n, dmamux_reg_offset),	\
 		DMA_MCUX_EDMA_CHANNEL_GAP(n)					\
+		.tcdpool = dma_tcdpool##n,					\
 	};									\
 										\
-	struct dma_mcux_edma_data dma_data_##n;					\
+	static struct call_back							\
+		dma_data_callback_##n[DT_INST_PROP(n, dma_channels)];		\
+	static ATOMIC_DEFINE(							\
+		dma_channels_atomic_##n, DT_INST_PROP(n, dma_channels));	\
+	static struct dma_mcux_edma_data dma_data_##n = {			\
+		.data_cb = dma_data_callback_##n,				\
+		.channels_atomic = dma_channels_atomic_##n,			\
+	};									\
 										\
 	DEVICE_DT_INST_DEFINE(n,						\
 			      &dma_mcux_edma_init, NULL,			\

diff --git a/dts/arm/nxp/nxp_s32z27x_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_r52.dtsi
@@ -1116,5 +1116,134 @@
 			clock-frequency = <I2C_BITRATE_STANDARD>;
 			status = "disabled";
 		};
+
+		edma0: dma-controller@405d0000 {
+			compatible = "nxp,mcux-edma-v3";
+			reg = <0x405d0000 0x10000>, <0x405a0000 0x10000>, <0x405b0000 0x100000>;
+			dma-channels = <32>;
+			dma-requests = <64>;
+			dmamux-reg-offset = <3>;
+			#dma-cells = <2>;
+			nxp,mem2mem;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 32 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 33 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 34 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 35 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 36 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 37 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 38 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 39 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 40 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 42 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 43 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 44 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 45 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 46 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 47 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 48 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 49 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 50 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 51 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 52 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 53 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 54 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 55 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 56 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 57 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 58 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 59 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 60 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 61 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 62 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 28 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
+
+		edma1: dma-controller@40dd0000 {
+			compatible = "nxp,mcux-edma-v3";
+			reg = <0x40dd0000 0x10000>, <0x40da0000 0x10000>;
+			dma-channels = <16>;
+			dma-requests = <64>;
+			dmamux-reg-offset = <3>;
+			#dma-cells = <2>;
+			nxp,mem2mem;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 66 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 67 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 68 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 69 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 70 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 71 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 72 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 73 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 74 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 75 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 76 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 77 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 78 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 79 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 80 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 63 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
+
+		edma4: dma-controller@425d0000 {
+			compatible = "nxp,mcux-edma-v3";
+			reg = <0x425d0000 0x10000>, <0x425a0000 0x10000>;
+			dma-channels = <32>;
+			dma-requests = <64>;
+			dmamux-reg-offset = <3>;
+			#dma-cells = <2>;
+			nxp,mem2mem;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 84 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 85 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 86 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 87 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 88 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 89 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 90 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 91 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 92 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 93 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 94 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 95 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 96 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 97 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 98 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 81 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
+
+		edma5: dma-controller@42dd0000 {
+			compatible = "nxp,mcux-edma-v3";
+			reg = <0x42dd0000 0x10000>, <0x42da0000 0x10000>;
+			dma-channels = <32>;
+			dma-requests = <64>;
+			dmamux-reg-offset = <3>;
+			#dma-cells = <2>;
+			nxp,mem2mem;
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 99 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
+
 	};
 };
diff --git a/soc/nxp/s32/s32ze/Kconfig b/soc/nxp/s32/s32ze/Kconfig
@@ -19,6 +19,7 @@ config SOC_SERIES_S32ZE
 	select HAS_MCUX_FLEXCAN
 	select HAS_MCUX_LPI2C
 	select SOC_EARLY_INIT_HOOK
+	select HAS_MCUX_EDMA
 
 if SOC_SERIES_S32ZE
 

diff --git a/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu0.conf b/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu0.conf
@@ -0,0 +1,4 @@
+CONFIG_DMA_TRANSFER_CHANNEL_NR_0=0
+CONFIG_DMA_TRANSFER_CHANNEL_NR_1=16
+CONFIG_CODE_DATA_RELOCATION=y
+CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAMNOCACHE"
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu0.overlay
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	soc {
+		sram_nocache: memory@31870000 {
+			compatible = "zephyr,memory-region", "mmio-sram";
+			reg = <0x31870000 DT_SIZE_K(64)>;
+			zephyr,memory-region = "SRAMNOCACHE";
+			zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE))>;
+		};
+	};
+};
+
+&sram0 {
+	compatible = "mmio-sram";
+	reg = <0x31780000 DT_SIZE_K(960)>;
+};
+
+&edma0 {
+	status = "okay";
+};
+
+tst_dma0: &edma0 { };
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu1.conf b/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu1.conf
@@ -0,0 +1,4 @@
+CONFIG_DMA_TRANSFER_CHANNEL_NR_0=0
+CONFIG_DMA_TRANSFER_CHANNEL_NR_1=15
+CONFIG_CODE_DATA_RELOCATION=y
+CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAMNOCACHE"
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/drivers/dma/chan_blen_transfer/boards/s32z2xxdc2_s32z270_rtu1.overlay
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	soc {
+		sram_nocache: memory@35870000 {
+			compatible = "zephyr,memory-region", "mmio-sram";
+			reg = <0x35870000 DT_SIZE_K(64)>;
+			zephyr,memory-region = "SRAMNOCACHE";
+			zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE))>;
+		};
+	};
+};
+
+&sram1 {
+	compatible = "mmio-sram";
+	reg = <0x35780000 DT_SIZE_K(960)>;
+};
+
+&edma5 {
+	status = "okay";
+};
+
+tst_dma0: &edma5 { };
-Original file line number
+Diff line change
@@ Expand Up / @@ -18,4 +18,5 @@ supported: @@
       - counter
       - adc
       - i2c
+      - dma
     vendor: nxp