Introduce Bouffalo Lab SoC's

modules/hal_bouffalolab/CMakeLists.txt

@@ -15,7 +15,7 @@ zephyr_library_compile_definitions(
   BFLB_USE_CUSTOM_LD_SECTIONS
 )
 
-set(bflb_soc         ${CONFIG_SOC_SUB_SERIES})
+set(bflb_soc         ${CONFIG_SOC_SERIES}02)
 set(bflb_drv_dir     ${ZEPHYR_HAL_BOUFFALOLAB_MODULE_DIR}/drivers/${bflb_soc}_driver)
 set(bflb_common_dir  ${ZEPHYR_HAL_BOUFFALOLAB_MODULE_DIR}/common)
 set(bflb_drv_src_dir ${bflb_drv_dir}/std_drv/src)

modules/hal_bouffalolab/include/bflb_glb.h

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2021-2024 Gerson Fernando Budke <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_HAL_BFLB_GLB_H_
+#define ZEPHYR_HAL_BFLB_GLB_H_
+
+#ifdef CONFIG_SOC_SERIES_BL6
+	#include <bl602_glb.h>
+#endif
+
+#endif	/* ZEPHYR_HAL_BFLB_GLB_H_ */

modules/hal_bouffalolab/include/bflb_hbn.h

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2021-2024 Gerson Fernando Budke <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_HAL_BFLB_HBN_H_
+#define ZEPHYR_HAL_BFLB_HBN_H_
+
+#ifdef CONFIG_SOC_SERIES_BL6
+	#include <bl602_hbn.h>
+#endif
+
+#endif	/* ZEPHYR_HAL_BFLB_HBN_H_ */

soc/bouffalolab/CMakeLists.txt

@@ -0,0 +1,6 @@
+# Copyright (c) 2021-2024 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(common)
+add_subdirectory(${SOC_SERIES})

soc/bouffalolab/Kconfig

@@ -0,0 +1,12 @@
+# Copyright (c) 2021-2024 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_BFLB
+	select HAS_BFLB_HAL
+
+if SOC_FAMILY_BFLB
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_BFLB

soc/bouffalolab/Kconfig.defconfig

@@ -0,0 +1,9 @@
+# Copyright (c) 2021-2024 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_BFLB
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_BFLB

soc/bouffalolab/Kconfig.soc

@@ -0,0 +1,11 @@
+# Copyright (c) 2021-2024 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_BFLB
+	bool
+
+config SOC_FAMILY
+	default "bflb" if SOC_FAMILY_BFLB
+
+rsource "*/Kconfig.soc"

soc/bouffalolab/bl6/CMakeLists.txt

@@ -0,0 +1,10 @@
+# Copyright (c) 2021-2024 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+zephyr_sources(soc.c)
+
+zephyr_linker_sources_ifdef(CONFIG_SOC_SERIES_BL6 RODATA rodata.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

soc/bouffalolab/bl6/Kconfig

@@ -0,0 +1,21 @@
+# Copyright (c) 2021-2024 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_BL6
+	select RISCV
+	select RISCV_HAS_CPU_IDLE
+	select RISCV_MACHINE_TIMER
+	select ATOMIC_OPERATIONS_C
+	select COMPRESSED_ISA
+	select CPU_HAS_FPU
+	select INCLUDE_RESET_VECTOR
+	select SOC_EARLY_INIT_HOOK
+	select XIP
+
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI

soc/bouffalolab/bl6/Kconfig.defconfig

@@ -0,0 +1,13 @@
+# Copyright (c) 2021-2024 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_BL6
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 192000000
+
+config NUM_IRQS
+	default 64
+
+endif   # SOC_SERIES_BL6

soc/bouffalolab/bl6/Kconfig.soc

@@ -0,0 +1,49 @@
+# Copyright (c) 2021-2024 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_BL6
+	bool
+	select SOC_FAMILY_BFLB
+	help
+	  Enable support for BouffaloLab BL6xx MCU series
+
+config SOC_SERIES
+	default "bl6" if SOC_SERIES_BL6
+
+config SOC_BL602C00Q2I
+	bool
+	select SOC_SERIES_BL6
+
+config SOC_BL602C20Q2I
+	bool
+	select SOC_SERIES_BL6
+
+config SOC_BL602C20Q2IS
+	bool
+	select SOC_SERIES_BL60X
+
+config SOC_BL602C40Q2IS
+	bool
+	select SOC_SERIES_BL60X
+
+config SOC_BL602l10Q2H
+	bool
+	select SOC_SERIES_BL60X
+
+config SOC_BL602l20Q2H
+	bool
+	select SOC_SERIES_BL60X
+
+config SOC_BL604E20Q2I
+	bool
+	select SOC_SERIES_BL6
+
+config SOC
+	default "bl602c00q2i"  if SOC_BL602C00Q2I
+	default "bl602c20q2i"  if SOC_BL602C20Q2I
+	default "bl602c20q2is" if SOC_BL602C20Q2IS
+	default "bl602c40q2is" if SOC_BL602C40Q2IS
+	default "bl602l10q2h"  if SOC_BL602l10Q2H
+	default "bl602l20q2h"  if SOC_BL602l20Q2H
+	default "bl604e20q2i"  if SOC_BL604E20Q2I

soc/bouffalolab/bl6/rodata.ld

@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2021-2024 ATL Electronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+KEEP(*(SORT_NONE( EXCLUDE_FILE( *bl602_glb.o	\
+				*bl602_pds.o	\
+				*bl602_common.o \
+				*bl602_sf_cfg.o \
+				*bl602_sf_cfg_ext*.o* \
+				*bl602_sf_ctrl.o \
+				*bl602_sflash.o \
+				*bl602_sflash_ext*.o* \
+				*bl602_xip_sflash.o \
+				*bl602_xip_sflash_ext*.o* \
+				*bl602_ef_ctrl.o) .rodata*)))

soc/bouffalolab/bl6/soc.c

@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2021-2024 ATL Electronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Bouffalo Lab RISC-V MCU series initialization code
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/irq.h>
+
+#include <bflb_hbn.h>
+#include <bflb_glb.h>
+#include <clic.h>
+
+/* clang-format off */
+
+#define ROOT_FCLK_DIV			(0)
+#define ROOT_BCLK_DIV			(1)
+#define ROOT_UART_CLOCK_DIV		(0)
+
+static void system_bor_init(void)
+{
+	HBN_BOR_CFG_Type borCfg = { 1 /* pu_bor */, 0 /* irq_bor_en */,
+				    1 /* bor_vth */, 1 /* bor_sel */ };
+	HBN_Set_BOR_Cfg(&borCfg);
+}
+
+static uint32_t mtimer_get_clk_src_div(void)
+{
+	return ((SystemCoreClockGet() / (GLB_Get_BCLK_Div() + 1))
+		/ 1000 / 1000 - 1);
+}
+
+static void system_clock_init(void)
+{
+	GLB_Set_System_CLK(GLB_PLL_XTAL_40M, GLB_SYS_CLK_PLL160M);
+	GLB_Set_System_CLK_Div(ROOT_FCLK_DIV, ROOT_BCLK_DIV);
+	GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div());
+}
+
+static void peripheral_clock_init(void)
+{
+	GLB_Set_UART_CLK(1, HBN_UART_CLK_160M, ROOT_UART_CLOCK_DIV);
+}
+
+void soc_early_init_hook(void)
+{
+	uint32_t key;
+	uint32_t *p;
+	uint32_t i = 0;
+	uint32_t tmp = 0;
+
+	key = irq_lock();
+
+	__disable_irq();
+
+	/* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */
+	tmp = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+	tmp = BL_CLR_REG_BIT(tmp, HBN_REG_EN_HW_PU_PD);
+	BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmp);
+
+	/* GLB_Set_EM_Sel(GLB_EM_0KB); */
+	tmp = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
+	tmp = BL_SET_REG_BITS_VAL(tmp, GLB_EM_SEL, GLB_EM_0KB);
+	BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmp);
+
+	/* Fix 26M xtal clkpll_sdmin */
+	tmp = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
+
+	if (BL_GET_REG_BITS_VAL(tmp, PDS_CLKPLL_SDMIN) == 0x49D39D) {
+		tmp = BL_SET_REG_BITS_VAL(tmp, PDS_CLKPLL_SDMIN, 0x49D89E);
+		BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmp);
+	}
+
+	/* Restore default setting*/
+
+	/* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */
+	tmp = BL_RD_REG(GLB_BASE, GLB_PARM);
+	tmp = BL_SET_REG_BITS_VAL(tmp, GLB_UART_SWAP_SET, UART_SIG_SWAP_NONE);
+	BL_WR_REG(GLB_BASE, GLB_PARM, tmp);
+
+	/* GLB_JTAG_Sig_Swap_Set(JTAG_SIG_SWAP_NONE); */
+	tmp = BL_RD_REG(GLB_BASE, GLB_PARM);
+	tmp = BL_SET_REG_BITS_VAL(tmp, GLB_JTAG_SWAP_SET, JTAG_SIG_SWAP_NONE);
+	BL_WR_REG(GLB_BASE, GLB_PARM, tmp);
+
+	/* CLear all interrupt */
+	p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIE);
+
+	for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
+		p[i] = 0;
+	}
+
+	p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIP);
+
+	for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
+		p[i] = 0;
+	}
+
+	/* init bor for all platform */
+	system_bor_init();
+	/* global IRQ enable */
+	__enable_irq();
+
+	system_clock_init();
+	peripheral_clock_init();
+
+	irq_unlock(key);
+}
+
+/* identify flash config automatically */
+extern BL_Err_Type flash_init(void);
+
+void System_Post_Init(void)
+{
+	PDS_Trim_RC32M();
+	HBN_Trim_RC32K();
+	flash_init();
+}
+
+/* clang-format on */

soc/bouffalolab/bl6/soc.h

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2021-2024 ATL Electronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Board configuration macros
+ *
+ * This header file is used to specify and describe board-level aspects
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+#include <zephyr/sys/util.h>
+#include <../common/soc_common.h>
+
+#ifndef _ASMLANGUAGE
+
+/* Add include for DTS generated information */
+#include <zephyr/devicetree.h>
+
+#if defined(CONFIG_SOC_SERIES_BL6)
+#include <bl602.h>
+#else
+#error Library does not support the specified device.
+#endif
+
+/* clang-format off */
+
+/* RISC-V Machine Timer configuration */
+#define RISCV_MTIME_BASE                  0x0200BFF8
+#define RISCV_MTIMECMP_BASE               0x02004000
+
+/* lib-c hooks required RAM defined variables */
+#define RISCV_RAM_BASE                    DT_SRAM_BASE_ADDRESS
+#define RISCV_RAM_SIZE                    KB(DT_SRAM_SIZE)
+
+#define SOC_BOUFFALOLAB_BL_PLL160_FREQ_HZ (160000000)
+#define SOC_BOUFFALOLAB_BL_HCLK_FREQ_HZ	\
+		DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
+
+/* clang-format on */
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _SOC__H_ */

soc/bouffalolab/common/CMakeLists.txt

@@ -0,0 +1,11 @@
+# Copyright (c) 2021-2024 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+  soc_irq.S
+  soc_common_irq.c
+  vector.S
+  )