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drivers: flash: flash_mcux_flexspi: add support for W25Q512NW-IQ/IN #80017

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Merged
mmahadevan108 merged 2 commits into from
Nov 5, 2024
Merged

drivers: flash: flash_mcux_flexspi: add support for W25Q512NW-IQ/IN #80017

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33aa99a
drivers: flash: flash_mcux_flexspi: add support for W25Q512NW-IQ/IN
danieldegrasse Oct 16, 2024
70b5dc8
soc: nxp: imxrt: correct flexspi XIP check to avoid reclocking
danieldegrasse Oct 16, 2024
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38 changes: 38 additions & 0 deletions drivers/flash/flash_mcux_flexspi_nor.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1005,9 +1005,47 @@
flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
/* Device uses bit 1 of status reg 2 for QE */

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drivers/flash/flash_mcux_flexspi_nor.c:1008 
-		flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
-				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
-				kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
-		flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
-				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xDC,
-				kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32),
+		flexspi_lut[ERASE_SECTOR][0] =
+			FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
+					kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
+		flexspi_lut[ERASE_BLOCK][0] =
+			FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xDC,
+					kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32),
 		/* Read instruction used for polling is 0x05 */
-		data->legacy_poll = true;
-		flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
-				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
-				kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
+			data->legacy_poll = true;
+		flexspi_lut[READ_STATUS_REG][0] =
+			FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
+					kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);

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drivers/flash/flash_mcux_flexspi_nor.c:1008 
-		flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
-				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
-				kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
-		flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
-				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xDC,
-				kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32),
+		flexspi_lut[ERASE_SECTOR][0] =
+			FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
+					kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
+		flexspi_lut[ERASE_BLOCK][0] =
+			FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xDC,
+					kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32),
 		/* Read instruction used for polling is 0x05 */
-		data->legacy_poll = true;
-		flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
-				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
-				kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
+			data->legacy_poll = true;
+		flexspi_lut[READ_STATUS_REG][0] =
+			FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
+					kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
return flash_flexspi_nor_quad_enable(data, flexspi_lut,
JESD216_DW15_QER_VAL_S2B1v5);
case 0x60ef:
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@de-nordic de-nordic Oct 25, 2024

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I have just noticed that device identification here is done by two bytes only, which is not correct.
The W25Q512 IQ, full id 0xef6020 or 0xef8020 (the second bytes indicate QE fixed/select), has the same two bytes as w25Q128 0xef6019.
This means that the below identification may by mistake set 4 byte address config to 3 byte address device, which neither supports 133MHz operation nor configured commands.

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@danieldegrasse danieldegrasse Oct 25, 2024

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Good catch- would you like me to add a commit to this PR extending the device ID check for all the flash chips here?

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@de-nordic de-nordic Oct 26, 2024

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I think that this can be too much of a change for this PR, just add if within case to filter out the w25Q128, using the last byte, or configure it properly.
I do not think it is proper to fix everything in this PR and you will have to go through docs to gather info which will probably delay the PR till you are ready.

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@danieldegrasse danieldegrasse Oct 26, 2024

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Ok, I've added a check to skip configuration if the full ID does not match the W25Q512NW. I don't have hardware to verify on at the moment, but reading the datasheet I believe the vendor ID should be read as 0x2060ef

if ((vendor_id & 0xFFFFFF) != 0x2060ef) {
/*
* This is not the correct flash chip, and will not
* support the LUT table. Return here
*/
return -ENOTSUP;
}
/* W25Q512NW-IQ/IN flash, use 4 byte read/write */
flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
/* Flash needs 8 dummy cycles (at 133MHz) */
flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 8,
kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04);
/* Only 1S-1S-4S page program supported */
flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_4_4B,
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
/* Update ERASE commands for 4 byte mode */
flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(

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drivers/flash/flash_mcux_flexspi_nor.c:1038 
-		flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
-				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
-				kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
+		flexspi_lut[READ][0] =
+			FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
+					kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
 		/* Flash needs 8 dummy cycles (at 133MHz) */
-		flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
-				kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 8,
-				kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04);
+		flexspi_lut[READ][1] =
+			FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 8,
+					kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04);
 		/* Only 1S-1S-4S page program supported */
 		flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
-				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_4_4B,
-				kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
-		flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
-				kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
-				kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
+			kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_4_4B,
+			kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
+		flexspi_lut[PAGE_PROGRAM][1] =
+			FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
+					kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
 		/* Update ERASE commands for 4 byte mode */
-		flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
-				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
-				kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
+		flexspi_lut[ERASE_SECTOR][0] =
+			FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
+					kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);

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drivers/flash/flash_mcux_flexspi_nor.c:1038 
-		flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
-				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
-				kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
+		flexspi_lut[READ][0] =
+			FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
+					kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
 		/* Flash needs 8 dummy cycles (at 133MHz) */
-		flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
-				kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 8,
-				kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04);
+		flexspi_lut[READ][1] =
+			FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 8,
+					kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04);
 		/* Only 1S-1S-4S page program supported */
 		flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
-				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_4_4B,
-				kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
-		flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
-				kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
-				kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
+			kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_4_4B,
+			kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
+		flexspi_lut[PAGE_PROGRAM][1] =
+			FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
+					kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
 		/* Update ERASE commands for 4 byte mode */
-		flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
-				kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
-				kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
+		flexspi_lut[ERASE_SECTOR][0] =
+			FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
+					kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xDC,
kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32),
/* Read instruction used for polling is 0x05 */
data->legacy_poll = true;
flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
/* Device uses bit 1 of status reg 2 for QE */
return flash_flexspi_nor_quad_enable(data, flexspi_lut,
JESD216_DW15_QER_VAL_S2B1v5);
case 0x25C2:
/* MX25 flash, use 4 byte read/write */
flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
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2 changes: 1 addition & 1 deletion soc/nxp/imxrt/imxrt11xx/soc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -559,8 +559,8 @@
#endif
#endif

#if !(DT_NODE_HAS_COMPAT(DT_CHOSEN(zephyr_flash), nxp_imx_flexspi)) && \
#if !(DT_NODE_HAS_COMPAT(DT_PARENT(DT_CHOSEN(zephyr_flash)), nxp_imx_flexspi)) && \
defined(CONFIG_MEMC_MCUX_FLEXSPI) && DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexspi))

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soc/nxp/imxrt/imxrt11xx/soc.c:563 
-#if !(DT_NODE_HAS_COMPAT(DT_PARENT(DT_CHOSEN(zephyr_flash)), nxp_imx_flexspi)) &&  \
+#if !(DT_NODE_HAS_COMPAT(DT_PARENT(DT_CHOSEN(zephyr_flash)), nxp_imx_flexspi)) &&                  \

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soc/nxp/imxrt/imxrt11xx/soc.c:563 
-#if !(DT_NODE_HAS_COMPAT(DT_PARENT(DT_CHOSEN(zephyr_flash)), nxp_imx_flexspi)) &&  \
+#if !(DT_NODE_HAS_COMPAT(DT_PARENT(DT_CHOSEN(zephyr_flash)), nxp_imx_flexspi)) &&                  \
/* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */
rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2;
rootCfg.div = 1;
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