boards: seeed: add XIAO ESP32C6 support

boards/seeed/xiao_esp32c6/Kconfig

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+# Copyright (c) 2024 Mario Paja
+# SPDX-License-Identifier: Apache-2.0
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+	int
+	default 4096

boards/seeed/xiao_esp32c6/Kconfig.sysbuild

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+# Copyright (c) 2024 Mario Paja
+# SPDX-License-Identifier: Apache-2.0
+
+choice BOOTLOADER
+	default BOOTLOADER_MCUBOOT
+endchoice
+
+choice BOOT_SIGNATURE_TYPE
+	default BOOT_SIGNATURE_TYPE_NONE
+endchoice

boards/seeed/xiao_esp32c6/Kconfig.xiao_esp32c6

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+# XIAO ESP32C6 board configuration
+
+# Copyright (c) 2024 Mario Paja
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_XIAO_ESP32C6
+	select SOC_ESP32_C6_WROOM_1U_N4

boards/seeed/xiao_esp32c6/board.cmake

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+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
+  set(OPENOCD OPENOCD-NOTFOUND)
+endif()
+find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
+
+include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/seeed/xiao_esp32c6/board.yml

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+board:
+  name: xiao_esp32c6
+  full_name: XIAO ESP32C6
+  vendor: seeed
+  socs:
+  - name: esp32c6

boards/seeed/xiao_esp32c6/doc/index.rst

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+.. zephyr:board:: xiao_esp32c6
+
+Overview
+********
+
+Seeed Studio XIAO ESP32C6 is powered by the highly-integrated ESP32-C6 SoC.
+It consists of a high-performance (HP) 32-bit RISC-V processor, which can be clocked up to 160 MHz,
+and a low-power (LP) 32-bit RISC-V processor, which can be clocked up to 20 MHz.
+It has a 320KB ROM, a 512KB SRAM, and works with external flash.
+This board integrates complete Wi-Fi, Bluetooth LE, Zigbee, and Thread functions.
+For more information, check `Seeed Studio XIAO ESP32C6`_ .
+
+Hardware
+********
+
+This board is based on the ESP32-C6 with 4MB of flash, integrating 2.4 GHz Wi-Fi 6,
+Bluetooth 5.3 (LE) and the 802.15.4 protocol. It has an USB-C port for programming
+and debugging, integrated battery charging and an U.FL external antenna connector.
+It is based on a standard XIAO 14 pin pinout.
+
+Supported Features
+==================
+
+The Zephyr ``xiao_esp32c6`` board target supports the following hardware features:
+
++------------+------------+-------------------------------------+
+| Interface  | Controller | Driver/Component                    |
++============+============+=====================================+
+| UART       | on-chip    | serial port                         |
++------------+------------+-------------------------------------+
+| GPIO       | on-chip    | gpio                                |
++------------+------------+-------------------------------------+
+| PINMUX     | on-chip    | pinmux                              |
++------------+------------+-------------------------------------+
+| USB-JTAG   | on-chip    | hardware interface                  |
++------------+------------+-------------------------------------+
+| SPI Master | on-chip    | spi                                 |
++------------+------------+-------------------------------------+
+| Watchdog   | on-chip    | watchdog                            |
++------------+------------+-------------------------------------+
+| LEDC       | on-chip    | pwm                                 |
++------------+------------+-------------------------------------+
+| SPI DMA    | on-chip    | spi                                 |
++------------+------------+-------------------------------------+
+| GDMA       | on-chip    | dma                                 |
++------------+------------+-------------------------------------+
+| TRNG       | on-chip    | entropy                             |
++------------+------------+-------------------------------------+
+| USB-CDC    | on-chip    | serial                              |
++------------+------------+-------------------------------------+
+| Wi-Fi      | on-chip    |                                     |
++------------+------------+-------------------------------------+
+
+The board uses a standard XIAO pinout, the default pin mapping is the following:
+
+.. figure:: img/xiao_esp32c6_pinout.webp
+   :align: center
+   :alt: XIAO ESP32C6 Pinout
+
+   XIAO ESP32C6 Pinout
+
+System requirements
+*******************
+
+Prerequisites
+=============
+
+Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
+below to retrieve those files.
+
+.. code-block:: console
+
+   west blobs fetch hal_espressif
+
+.. note::
+
+   It is recommended running the command above after :file:`west update`.
+
+Building & Flashing
+*******************
+
+Simple boot
+===========
+
+The board could be loaded using the single binary image, without 2nd stage bootloader.
+It is the default option when building the application without additional configuration.
+
+.. note::
+
+   Simple boot does not provide any security features nor OTA updates.
+
+MCUboot bootloader
+==================
+
+User may choose to use MCUboot bootloader instead. In that case the bootloader
+must be built (and flashed) at least once.
+
+There are two options to be used when building an application:
+
+1. Sysbuild
+2. Manual build
+
+.. note::
+
+   User can select the MCUboot bootloader by adding the following line
+   to the board default configuration file.
+
+   .. code:: cfg
+
+      CONFIG_BOOTLOADER_MCUBOOT=y
+
+Sysbuild
+========
+
+The sysbuild makes possible to build and flash all necessary images needed to
+bootstrap the board with the EPS32 SoC.
+
+To build the sample application using sysbuild use the command:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/hello_world
+   :board: xiao_esp32c6
+   :goals: build
+   :west-args: --sysbuild
+   :compact:
+
+By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
+images. But it can be configured to create other kind of images.
+
+Build directory structure created by sysbuild is different from traditional
+Zephyr build. Output is structured by the domain subdirectories:
+
+.. code-block::
+
+  build/
+  ├── hello_world
+  │   └── zephyr
+  │       ├── zephyr.elf
+  │       └── zephyr.bin
+  ├── mcuboot
+  │    └── zephyr
+  │       ├── zephyr.elf
+  │       └── zephyr.bin
+  └── domains.yaml
+
+.. note::
+
+   With ``--sysbuild`` option the bootloader will be re-build and re-flash
+   every time the pristine build is used.
+
+For more information about the system build please read the :ref:`sysbuild` documentation.
+
+Manual build
+============
+
+During the development cycle, it is intended to build & flash as quickly possible.
+For that reason, images can be built one at a time using traditional build.
+
+The instructions following are relevant for both manual build and sysbuild.
+The only difference is the structure of the build directory.
+
+.. note::
+
+   Remember that bootloader (MCUboot) needs to be flash at least once.
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: xiao_esp32c6
+   :goals: build
+
+The usual ``flash`` target will work with the ``xiao_esp32c6`` board
+configuration. Here is an example for the :zephyr:code-sample:`hello_world`
+application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: xiao_esp32c6
+   :goals: flash
+
+Since the Zephyr console is by default on the ``usb_serial`` device, we use
+the espressif monitor to view.
+
+.. code-block:: console
+
+   $ west espressif monitor
+
+After the board has automatically reset and booted, you should see the following
+message in the monitor:
+
+.. code-block:: console
+
+   ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
+   Hello World! xiao_esp32c6/esp32c6
+
+Debugging
+*********
+
+As with much custom hardware, the ESP32-C6 modules require patches to
+OpenOCD that are not upstreamed yet. Espressif maintains their own fork of
+the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_.
+
+The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the
+``-DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>``
+parameter when building.
+
+Here is an example for building the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: xiao_esp32c6
+   :goals: build flash
+   :gen-args: -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
+
+You can debug an application in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: xiao_esp32c6
+   :goals: debug
+
+References
+**********
+
+.. target-notes::
+
+.. _`Seeed Studio XIAO ESP32C6`: https://wiki.seeedstudio.com/xiao_esp32c6_getting_started/
+.. _`ESP32-C6 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf
+.. _`ESP32-C6 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c6_technical_reference_manual_en.pdf
+.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases

boards/seeed/xiao_esp32c6/seeed_xiao_connector.dtsi

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+/*
+ * Copyright (c) 2024 Mario Paja
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	xiao_d: connector {
+		compatible = "seeed,xiao-gpio";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpio0 0 0>,	/* D0 */
+			   <1 0 &gpio0 1 0>,	/* D1 */
+			   <2 0 &gpio0 2 0>,	/* D2 */
+			   <3 0 &gpio0 21 0>,	/* D3 */
+			   <4 0 &gpio0 22 0>,	/* D4 */
+			   <5 0 &gpio0 23 0>,	/* D5 */
+			   <6 0 &gpio0 16 0>,	/* D6 */
+			   <7 0 &gpio0 17 0>,	/* D7 */
+			   <8 0 &gpio0 19 0>,	/* D8 */
+			   <9 0 &gpio0 20 0>,	/* D9 */
+			   <10 0 &gpio0 18 0>;	/* D10 */
+	};
+};
+
+xiao_spi: &spi2 {};
+xiao_serial: &uart0 {};

boards/seeed/xiao_esp32c6/support/openocd.cfg

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+# ESP32C6 has built-in JTAG interface over USB port in pins GPIO13/GPIO12 (D-/D+).
+set ESP_RTOS none
+
+source [find board/esp32c6-builtin.cfg]

boards/seeed/xiao_esp32c6/xiao_esp32c6-pinctrl.dtsi

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+/*
+ * Copyright (c) 2024 Mario Paja
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
+#include <dt-bindings/pinctrl/esp32c6-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/esp32c6-gpio-sigmap.h>
+
+&pinctrl {
+
+	uart0_default: uart0_default {
+		group1 {
+			pinmux = <UART0_TX_GPIO16>;
+			output-high;
+		};
+		group2 {
+			pinmux = <UART0_RX_GPIO17>;
+			bias-pull-up;
+		};
+	};
+
+	spim2_default: spim2_default {
+		group1 {
+			pinmux = <SPIM2_MISO_GPIO20>,
+				 <SPIM2_SCLK_GPIO19>;
+		};
+		group2 {
+			pinmux = <SPIM2_MOSI_GPIO18>;
+			output-low;
+		};
+	};
+};