drivers: pwm: nrfx: adjust PWM driver to fast PWM120 #80672

mstasiaknordic · 2024-10-31T10:25:11Z

Fast PWM120 instance works with 320MHz clock, thus pwm_nrfx_get_cycles_per_sec needs to be adjusted.
Also, it uses cachable RAM, thus sys_cache function needs to be added to flush the cached sequence.

Fast PWM120 instance works with 320MHz clock, thus pwm_nrfx_get_cycles_per_sec needs to be adjusted. Also, it uses cachable RAM, thus sys_cache function needs to be added to flush the cached sequence. Upstream PR : zephyrproject-rtos/zephyr#80672 Signed-off-by: Michał Stasiak <[email protected]>

Fast PWM120 instance works with 320MHz clock, thus pwm_nrfx_get_cycles_per_sec needs to be adjusted. Also, it uses cachable RAM, thus sys_cache function needs to be added to flush the cached sequence. Upstream PR #: zephyrproject-rtos/zephyr#80672 Signed-off-by: Michał Stasiak <[email protected]>

nika-nordic · 2024-10-31T10:44:36Z

drivers/pwm/pwm_nrfx.c

I think we need to check in runtime whether d-cache operation is needed or not, depending on seq.values.p_raw memory region attributes. You can take inspiration from this PR: https://github.com/zephyrproject-rtos/zephyr/pull/80015/files , see UARTE_IS_CACHEABLE .

Maybe in the future we could switch to dmm for this shim, but let's it keep simple as this is hotfix

masz-nordic · 2024-10-31T11:31:36Z

drivers/pwm/pwm_nrfx.c

How about using this approach from UARTE:
036a85b
7c01174

Since it is a hotfix, could we postpone the changes until the DMM rework?

I don't see connection between this and DMM, but I'm fine with this staying temporarily if you post a follow-up PR.

gmarull · 2024-10-31T11:58:30Z

drivers/pwm/pwm_nrfx.c

Suggested change

#ifdef CONFIG_NRFX_PWM120

*cycles = 320ul * 1000ul * 1000ul;

#else

#ifdef CONFIG_NRFX_PWM120

*cycles = 320ul * 1000ul * 1000ul;

#else

this won't work when enabling multiple instances.

I believe current solution will do, though it can be replaced with suitable macro introduced in future nrfx release

gmarull · 2024-10-31T13:04:32Z

drivers/pwm/pwm_nrfx.c

-1, please, describe clock in DT and capture it, it is actually straightforward.

I am affraid that would require adding clock property to every nrf pwm node. If thats not an issue, then sure.

all that need it, yes. Just check the UART case.

@gmarull won't it imply tree-wide change in all PWM nodes, in nRF52/53/91 devices as well? we wanted to avoid it

it can be made optional, see

zephyr/drivers/serial/uart_nrfx_uarte.c

Lines 2290 to 2294 in 124aae3

#define UARTE_GET_FREQ(idx) DT_PROP(DT_CLOCKS_CTLR(UARTE(idx)), clock_frequency)

#define UARTE_GET_BAUDRATE_DIV(idx) \

COND_CODE_1(DT_CLOCKS_HAS_IDX(UARTE(idx), 0), \

((UARTE_GET_FREQ(idx) / NRF_UARTE_BASE_FREQUENCY_16MHZ)), (1))

drivers/pwm/pwm_nrfx.c

dts/common/nordic/nrf54h20.dtsi

drivers/pwm/pwm_nrfx.c

dt looks ok

drivers/pwm/pwm_nrfx.c

Added hsfll120 clock for fast PWM120 nodes. Signed-off-by: Michał Stasiak <[email protected]>

Fast PWM120 instance works with 320MHz clock, thus pwm_nrfx_get_cycles_per_sec needs to be adjusted, applying correct clock frequency. Also, it uses cachable RAM, thus sys_cache function needs to be added to flush the cached sequence. Signed-off-by: Michał Stasiak <[email protected]>

Add pin retenion if GPD is enabled for nRF54H20. Signed-off-by: Michał Stasiak <[email protected]>

zephyrbot added area: PWM Pulse Width Modulation platform: nRF Nordic nRFx labels Oct 31, 2024

zephyrbot requested review from anangl, henrikbrixandersen, jaz1-nordic, kl-cruz, magp-nordic, masz-nordic and nika-nordic October 31, 2024 10:25

zephyrbot assigned anangl and masz-nordic Oct 31, 2024

mstasiaknordic mentioned this pull request Oct 31, 2024

[nrf fromlist] drivers: pwm: nrfx: adjust PWM driver to fast PWM120 nrfconnect/sdk-zephyr#2209

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mstasiaknordic added 3 commits November 13, 2024 10:52

dts: common: nordic: Add clock property for fast PWM120

8ca6473

Added hsfll120 clock for fast PWM120 nodes. Signed-off-by: Michał Stasiak <[email protected]>

drivers: pwm: nrfx: add pin retention

f31e675

Add pin retenion if GPD is enabled for nRF54H20. Signed-off-by: Michał Stasiak <[email protected]>

mstasiaknordic dismissed stale reviews from nika-nordic and anangl via f31e675 November 13, 2024 09:52

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nordic-segl approved these changes Nov 27, 2024

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nika-nordic approved these changes Dec 2, 2024

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kartben merged commit d04b3e0 into zephyrproject-rtos:main Dec 2, 2024
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mstasiaknordic deleted the fast_nrf_pwm branch January 2, 2025 07:40

-#ifdef CONFIG_NRFX_PWM120
-	*cycles = 320ul * 1000ul * 1000ul;
-#else
+#ifdef CONFIG_NRFX_PWM120
+	*cycles = 320ul * 1000ul * 1000ul;
+#else

	#define UARTE_GET_FREQ(idx) DT_PROP(DT_CLOCKS_CTLR(UARTE(idx)), clock_frequency)

	#define UARTE_GET_BAUDRATE_DIV(idx) \
	COND_CODE_1(DT_CLOCKS_HAS_IDX(UARTE(idx), 0), \
	((UARTE_GET_FREQ(idx) / NRF_UARTE_BASE_FREQUENCY_16MHZ)), (1))

drivers: pwm: nrfx: adjust PWM driver to fast PWM120 #80672

drivers: pwm: nrfx: adjust PWM driver to fast PWM120 #80672

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