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drivers: adc: microchip: Different channels per package type #80933

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Merged
kartben merged 1 commit into from
Dec 11, 2024
Merged

drivers: adc: microchip: Different channels per package type #80933

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9 changes: 5 additions & 4 deletions drivers/adc/adc_mchp_xec.c
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Original file line number Diff line number Diff line change
Expand Up @@ -47,15 +47,16 @@ enum adc_pm_policy_state_flag {
ADC_PM_POLICY_STATE_FLAG_COUNT,
};

#define XEC_ADC_CFG_CHANNELS DT_INST_PROP(0, channels)

struct adc_xec_regs {
uint32_t control_reg;
uint32_t delay_reg;
uint32_t status_reg;
uint32_t single_reg;
uint32_t repeat_reg;
uint32_t channel_read_reg[8];
uint32_t unused[18];
uint32_t channel_read_reg[XEC_ADC_CFG_CHANNELS];
uint32_t unused[10 + (MCHP_ADC_MAX_CHAN - XEC_ADC_CFG_CHANNELS)];
uint32_t config_reg;
uint32_t vref_channel_reg;
uint32_t vref_control_reg;
Expand Down Expand Up @@ -139,7 +140,7 @@ static int adc_xec_channel_setup(const struct device *dev,
return -EINVAL;
}

if (channel_cfg->channel_id >= MCHP_ADC_MAX_CHAN) {
if (channel_cfg->channel_id >= XEC_ADC_CFG_CHANNELS) {
return -EINVAL;
}

Expand Down Expand Up @@ -205,7 +206,7 @@ static int adc_xec_start_read(const struct device *dev,
struct adc_xec_data * const data = dev->data;
uint32_t sar_ctrl;

if (sequence->channels & ~BIT_MASK(MCHP_ADC_MAX_CHAN)) {
if (sequence->channels & ~BIT_MASK(XEC_ADC_CFG_CHANNELS)) {
LOG_ERR("Incorrect channels, bitmask 0x%x", sequence->channels);
return -EINVAL;
}
Expand Down
1 change: 1 addition & 0 deletions dts/arm/microchip/mec1501hsz.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -442,6 +442,7 @@
status = "disabled";
#io-channel-cells = <1>;
clktime = <32>;
channels = <8>;
};
kbd0: kbd@40009c00 {
compatible = "microchip,xec-kbd";
Expand Down
1 change: 1 addition & 0 deletions dts/arm/microchip/mec172x_common.dtsi
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Expand Up @@ -650,6 +650,7 @@ adc0: adc@40007c00 {
status = "disabled";
#io-channel-cells = <1>;
clktime = <32>;
channels = <16>;
};
kbd0: kbd@40009c00 {
compatible = "microchip,xec-kbd";
Expand Down
4 changes: 4 additions & 0 deletions dts/arm/microchip/mec172xnsz.dtsi
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Expand Up @@ -75,3 +75,7 @@
&systick {
status = "disabled";
};

&adc0 {
channels = <8>;
};
5 changes: 5 additions & 0 deletions dts/bindings/adc/microchip,xec-adc.yaml
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Expand Up @@ -33,6 +33,11 @@ properties:
required: true
description: ADC clock high & low time count value <1:255>

channels:
type: int
required: true
description: Number of ADC channels supported by SoC

pinctrl-0:
required: true

Expand Down
36 changes: 34 additions & 2 deletions soc/microchip/mec/common/reg/mec_adc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -10,9 +10,15 @@
#include <stdint.h>
#include <stddef.h>

#if defined(CONFIG_SOC_MEC172X_NLJ)
/* 16 ADC channels numbered 0 - 15 */
#define MCHP_ADC_MAX_CHAN 16u
#define MCHP_ADC_MAX_CHAN_MASK 0x0fu
#else

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soc/microchip/mec/common/reg/mec_adc.h:17 
-#define MCHP_ADC_MAX_CHAN		16u
-#define MCHP_ADC_MAX_CHAN_MASK		0x0fu
+#define MCHP_ADC_MAX_CHAN      16u
+#define MCHP_ADC_MAX_CHAN_MASK 0x0fu
/* Eight ADC channels numbered 0 - 7 */
#define MCHP_ADC_MAX_CHAN 8u
#define MCHP_ADC_MAX_CHAN_MASK 0x07u
#endif

/* Control register */
#define MCHP_ADC_CTRL_REG_OFS 0u
Expand Down Expand Up @@ -42,15 +48,27 @@

/* Single Conversion Select register */
#define MCHP_ADC_SCS_REG_OFS 0x0cu
#if defined(CONFIG_SOC_MEC172X_NLJ)
#define MCHP_ADC_SCS_REG_MASK 0xffffu
#define MCHP_ADC_SCS_CH_0_15 0xffffu
#define MCHP_ADC_SCS_CH(n) BIT(((n) & 0x0fu))
#else

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soc/microchip/mec/common/reg/mec_adc.h:55 
-#define MCHP_ADC_SCS_REG_MASK		0xffffu
-#define MCHP_ADC_SCS_CH_0_15		0xffffu
-#define MCHP_ADC_SCS_CH(n)		BIT(((n) & 0x0fu))
+#define MCHP_ADC_SCS_REG_MASK 0xffffu
+#define MCHP_ADC_SCS_CH_0_15  0xffffu
+#define MCHP_ADC_SCS_CH(n)    BIT(((n) & 0x0fu))
#define MCHP_ADC_SCS_REG_MASK 0xffu
#define MCHP_ADC_SCS_CH_0_7 0xffu
#define MCHP_ADC_SCS_CH(n) BIT(((n) & 0x07u))
#endif

/* Repeat Conversion Select register */
#define MCHP_ADC_RCS_REG_OFS 0x10u
#if defined(CONFIG_SOC_MEC172X_NLJ)
#define MCHP_ADC_RCS_REG_MASK 0xffffu
#define MCHP_ADC_RCS_CH_0_15 0xffffu
#define MCHP_ADC_RCS_CH(n) BIT(((n) & 0x0fu))
#else

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soc/microchip/mec/common/reg/mec_adc.h:67 
-#define MCHP_ADC_RCS_REG_MASK		0xffffu
-#define MCHP_ADC_RCS_CH_0_15		0xffffu
-#define MCHP_ADC_RCS_CH(n)		BIT(((n) & 0x0fu))
+#define MCHP_ADC_RCS_REG_MASK 0xffffu
+#define MCHP_ADC_RCS_CH_0_15  0xffffu
+#define MCHP_ADC_RCS_CH(n)    BIT(((n) & 0x0fu))
#define MCHP_ADC_RCS_REG_MASK 0xffu
#define MCHP_ADC_RCS_CH_0_7 0xffu
#define MCHP_ADC_RCS_CH(n) BIT(((n) & 0x07u))
#endif

/* Channel reading registers */
#define MCHP_ADC_RDCH_REG_MASK 0xfffu
Expand All @@ -62,7 +80,15 @@
#define MCHP_ADC_RDCH5_REG_OFS 0x28u
#define MCHP_ADC_RDCH6_REG_OFS 0x2cu
#define MCHP_ADC_RDCH7_REG_OFS 0x30u
#define MCHP_ADC_RDCH8_REG_OFS 0x34u
#define MCHP_ADC_RDCH9_REG_OFS 0x38u
#define MCHP_ADC_RDCH10_REG_OFS 0x3cu
#define MCHP_ADC_RDCH11_REG_OFS 0x40u
#define MCHP_ADC_RDCH12_REG_OFS 0x44u
#define MCHP_ADC_RDCH13_REG_OFS 0x48u
#define MCHP_ADC_RDCH14_REG_OFS 0x4cu
#define MCHP_ADC_RDCH15_REG_OFS 0x50u

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soc/microchip/mec/common/reg/mec_adc.h:91 
-#define MCHP_ADC_RDCH8_REG_OFS		0x34u
-#define MCHP_ADC_RDCH9_REG_OFS		0x38u
-#define MCHP_ADC_RDCH10_REG_OFS		0x3cu
-#define MCHP_ADC_RDCH11_REG_OFS		0x40u
-#define MCHP_ADC_RDCH12_REG_OFS		0x44u
-#define MCHP_ADC_RDCH13_REG_OFS		0x48u
-#define MCHP_ADC_RDCH14_REG_OFS		0x4cu
-#define MCHP_ADC_RDCH15_REG_OFS		0x50u
+#define MCHP_ADC_RDCH8_REG_OFS          0x34u
+#define MCHP_ADC_RDCH9_REG_OFS          0x38u
+#define MCHP_ADC_RDCH10_REG_OFS         0x3cu
+#define MCHP_ADC_RDCH11_REG_OFS         0x40u
+#define MCHP_ADC_RDCH12_REG_OFS         0x44u
+#define MCHP_ADC_RDCH13_REG_OFS         0x48u
+#define MCHP_ADC_RDCH14_REG_OFS         0x4cu
+#define MCHP_ADC_RDCH15_REG_OFS         0x50u
/* Configuration register */
#define MCHP_ADC_CFG_REG_OFS 0x7cu
#define MCHP_ADC_CFG_REG_MASK 0xffffu
Expand All @@ -76,9 +102,15 @@
/* Channel Vref Select register */
#define MCHP_ADC_CH_VREF_SEL_REG_OFS 0x80u
#define MCHP_ADC_CH_VREF_SEL_REG_MASK 0x00ffffffu
#if defined(CONFIG_SOC_MEC172X_NLJ)
#define MCHP_ADC_CH_VREF_SEL_MASK(n) SHLU32(0x03u, (((n) & 0x0f) * 2u))
#define MCHP_ADC_CH_VREF_SEL_PAD(n) 0u
#define MCHP_ADC_CH_VREF_SEL_GPIO(n) SHLU32(0x01u, (((n) & 0x0f) * 2u))
#else

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soc/microchip/mec/common/reg/mec_adc.h:109 
-#define MCHP_ADC_CH_VREF_SEL_MASK(n)	SHLU32(0x03u, (((n) & 0x0f) * 2u))
-#define MCHP_ADC_CH_VREF_SEL_PAD(n)	0u
-#define MCHP_ADC_CH_VREF_SEL_GPIO(n)	SHLU32(0x01u, (((n) & 0x0f) * 2u))
+#define MCHP_ADC_CH_VREF_SEL_MASK(n) SHLU32(0x03u, (((n) & 0x0f) * 2u))
+#define MCHP_ADC_CH_VREF_SEL_PAD(n)  0u
+#define MCHP_ADC_CH_VREF_SEL_GPIO(n) SHLU32(0x01u, (((n) & 0x0f) * 2u))
#define MCHP_ADC_CH_VREF_SEL_MASK(n) SHLU32(0x03u, (((n) & 0x07) * 2u))
#define MCHP_ADC_CH_VREF_SEL_PAD(n) 0u
#define MCHP_ADC_CH_VREF_SEL_GPIO(n) SHLU32(0x01u, (((n) & 0x07) * 2u))
#endif

/* Vref Control register */
#define MCHP_ADC_VREF_CTRL_REG_OFS 0x84u
Expand Down Expand Up @@ -131,8 +163,8 @@
volatile uint32_t STATUS;
volatile uint32_t SINGLE;
volatile uint32_t REPEAT;
volatile uint32_t RD[8];
uint8_t RSVD1[0x7c - 0x34];
volatile uint32_t RD[MCHP_ADC_MAX_CHAN];
uint8_t RSVD1[0x7c - ((MCHP_ADC_MAX_CHAN * 4) + 0x14)];
volatile uint32_t CONFIG;
volatile uint32_t VREF_CHAN_SEL;
volatile uint32_t VREF_CTRL;
Expand Down
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