boards: openhwgroup: add CVA6 Testbench #81017
Closed
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Adds support for the CVA6 CPU in the hardware simulation / testbench environment. Especially, configurations are added that allow the application to indicate success or error to the testbench. The SoC currently contains the CVA CPU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, a GPIO and the lowRISC ethernet subsystem (which is currently without a driver in zephyr). Two sample applications are provided, demonstrating how to indicate success or failure to the testbench. Signed-off-by: Eric Ackermann <[email protected]>
|
This pull request has been marked as stale because it has been open (more than) 60 days with no activity. Remove the stale label or add a comment saying that you would like to have the label removed otherwise this pull request will automatically be closed in 14 days. Note, that you can always re-open a closed pull request at any time. |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
3 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Adds support for the CVA6 CPU in the hardware simulation / testbench environment. Especially, configurations are added that allow the application to indicate success or error to the testbench. The SoC currently contains the CVA CPU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, a GPIO and the lowRISC ethernet subsystem (which is currently without a driver in zephyr).
Two sample applications are provided, demonstrating how to indicate success or failure to the testbench.