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Adds support for the CVA6 CPU on an Arty A7 FPGA board (https://github.com/openhwgroup/cva6).
The SoC currently contains the CVA6 CPU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, a GPIO and the lowRISC ethernet subsystem. Two slightly different versions of the board are added, with a 32-bit and a 64-bit configuration of CVA6, respectively.

Adds support for the CVA6 CPU on an Arty A7 FPGA board
(https://github.com/openhwgroup/cva6).
The SoC currently contains the CVA6 CPU, interrupt controllers (CLINT and PLIC),
UART, a SPI for booting from SD, a boot ROM, a GPIO and the lowRISC ethernet subsystem.
Two slightly different versions of the board are added, with a 32-bit
and a 64-bit configuration of CVA6, respectively.

Signed-off-by: Eric Ackermann <[email protected]>
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github-actions bot commented Jan 6, 2025

This pull request has been marked as stale because it has been open (more than) 60 days with no activity. Remove the stale label or add a comment saying that you would like to have the label removed otherwise this pull request will automatically be closed in 14 days. Note, that you can always re-open a closed pull request at any time.

@github-actions github-actions bot added the Stale label Jan 6, 2025
@github-actions github-actions bot closed this Jan 21, 2025
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