boards: openhwgroup: add CV64A6 on GenesysII board #81019
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Adds support for the CVA6 CPU on a GenesysII FPGA board forked by CISPA with Xilinx AXI Ethernet (https://github.com/cispa/CVA6-Vivado-Project-with-Xilinx-AXI-Ethernet). The SoC currently contains the CVA6 CPU in 64-bit configuration with the SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, and I2C controller for on-board audio, a GPIO and the Xilinx AXI Ethernet subsystem. Signed-off-by: Eric Ackermann <[email protected]>
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Adds support for the CVA6 CPU on a GenesysII FPGA board forked by CISPA with Xilinx AXI Ethernet
(https://github.com/cispa/CVA6-Vivado-Project-with-Xilinx-AXI-Ethernet). The SoC currently contains the CVA6 CPU in 64-bit configuration with the SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, and I2C controller for on-board audio, a GPIO and the Xilinx AXI Ethernet subsystem.