drivers: mipi_dbi: mipi_dbi_nxp_lcdic: allow config of timer bases #81245
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The NXP LCDIC peripheral contains two internal timers, with configurable periods. These times are used to determine delays within the peripheral, such as the reset and tearing enable signal delays. Allow these periods to be set within the devicetree for the peripheral. Raise the period where required for display drivers that need a value other than the reset setting Signed-off-by: Daniel DeGrasse <[email protected]>
Reset pulse count can be up to 512 before we would be unable to support it using the peripheral. Use a uint32_t for the count, so that even long reset pulses will still be calculated correctly. Add code to warn about reset pulse requests that are too long. Signed-off-by: Daniel DeGrasse <[email protected]>
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dleach02
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Nov 22, 2024
| status = "okay"; | ||
| nxp,swap-bytes; | ||
| /* Raise the timer0 ratio to enable longer reset delay */ | ||
| nxp,timer0-ratio = <15>; |
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LGTM but what dictates using a value of 15? Is that just because what it was before in the hardcoding?
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Yes- also this display driver uses a long reset pulse (100 ms) which requires us to increase the timer0 base value. The reset pulse is set in units of the "Timer 0 base", the period of which is calculated as 2^(timer0-ratio)/lcdic_freq. So raising this value lets us generate longer reset pulses.
dleach02
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Nov 22, 2024
EmilioCBen
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Nov 22, 2024
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Can't approve my own PR, reassigning to @dleach02 since this affects NXP driver only |
mmahadevan108
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Nov 22, 2024
decsny
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Nov 22, 2024
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The NXP LCDIC peripheral contains two internal timers, with configurable
periods. These times are used to determine delays within the peripheral,
such as the reset and tearing enable signal delays. Allow these periods
to be set within the devicetree for the peripheral.
Raise the period where required for display drivers that need a value
other than the reset setting