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Merged
merged 1 commit into from
May 6, 2025
Merged

stm32 flash read out protection rdp in a common file #81876

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79 changes: 1 addition & 78 deletions drivers/flash/flash_stm32.c
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Original file line number Diff line number Diff line change
Expand Up @@ -42,8 +42,6 @@ static const struct flash_parameters flash_stm32_parameters = {
#endif
};

static int flash_stm32_cr_lock(const struct device *dev, bool enable);

bool __weak flash_stm32_valid_range(const struct device *dev, off_t offset,
uint32_t len, bool write)
{
Expand Down Expand Up @@ -228,7 +226,7 @@ static int flash_stm32_write(const struct device *dev, off_t offset,
return rc;
}

static int flash_stm32_cr_lock(const struct device *dev, bool enable)
int flash_stm32_cr_lock(const struct device *dev, bool enable)
{
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);

Expand Down Expand Up @@ -288,81 +286,6 @@ static int flash_stm32_cr_lock(const struct device *dev, bool enable)
return rc;
}

int flash_stm32_option_bytes_lock(const struct device *dev, bool enable)
{
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);

#if defined(FLASH_OPTCR_OPTLOCK) /* F2, F4, F7 */
if (enable) {
regs->OPTCR |= FLASH_OPTCR_OPTLOCK;
} else if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) {
regs->OPTKEYR = FLASH_OPT_KEY1;
regs->OPTKEYR = FLASH_OPT_KEY2;
}
#else
int rc;

/* Unlock CR/PECR/NSCR register if needed. */
if (!enable) {
rc = flash_stm32_cr_lock(dev, false);
if (rc) {
return rc;
}
}
#if defined(FLASH_CR_OPTWRE) /* F0, F1 and F3 */
if (enable) {
regs->CR &= ~FLASH_CR_OPTWRE;
} else if (!(regs->CR & FLASH_CR_OPTWRE)) {
regs->OPTKEYR = FLASH_OPTKEY1;
regs->OPTKEYR = FLASH_OPTKEY2;
}
#elif defined(FLASH_CR_OPTLOCK) /* G0, G4, L4, WB and WL */
if (enable) {
regs->CR |= FLASH_CR_OPTLOCK;
} else if (regs->CR & FLASH_CR_OPTLOCK) {
regs->OPTKEYR = FLASH_OPTKEY1;
regs->OPTKEYR = FLASH_OPTKEY2;
}
#elif defined(FLASH_PECR_OPTLOCK) /* L0 and L1 */
if (enable) {
regs->PECR |= FLASH_PECR_OPTLOCK;
} else if (regs->PECR & FLASH_PECR_OPTLOCK) {
regs->OPTKEYR = FLASH_OPTKEY1;
regs->OPTKEYR = FLASH_OPTKEY2;
}
#elif defined(FLASH_NSCR_OPTLOCK) /* L5 and U5 */
if (enable) {
regs->NSCR |= FLASH_NSCR_OPTLOCK;
} else if (regs->NSCR & FLASH_NSCR_OPTLOCK) {
regs->OPTKEYR = FLASH_OPTKEY1;
regs->OPTKEYR = FLASH_OPTKEY2;
}
#elif defined(FLASH_NSCR1_OPTLOCK) /* WBA */
if (enable) {
regs->NSCR1 |= FLASH_NSCR1_OPTLOCK;
} else if (regs->NSCR1 & FLASH_NSCR1_OPTLOCK) {
regs->OPTKEYR = FLASH_OPTKEY1;
regs->OPTKEYR = FLASH_OPTKEY2;
}
#endif
/* Lock CR/PECR/NSCR register if needed. */
if (enable) {
rc = flash_stm32_cr_lock(dev, true);
if (rc) {
return rc;
}
}
#endif

if (enable) {
LOG_DBG("Option bytes locked");
} else {
LOG_DBG("Option bytes unlocked");
}

return 0;
}

#if defined(CONFIG_FLASH_EX_OP_ENABLED) && defined(CONFIG_FLASH_STM32_BLOCK_REGISTERS)
int flash_stm32_control_register_disable(const struct device *dev)
{
Expand Down
8 changes: 4 additions & 4 deletions drivers/flash/flash_stm32.h
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Original file line number Diff line number Diff line change
Expand Up @@ -55,6 +55,8 @@ struct flash_stm32_priv {
#define FLASH_CR_SNB FLASH_CR_SSN
#define FLASH_CR_SNB_Pos FLASH_CR_SSN_Pos
#define KEYR1 KEYR
#define FLASH_OPT_KEY1 FLASH_OPTKEY1
#define FLASH_OPT_KEY2 FLASH_OPTKEY2
#endif /* CONFIG_SOC_SERIES_STM32H7RSX */

/* Differentiate between arm trust-zone non-secure/secure, and others. */
Expand All @@ -71,11 +73,9 @@ struct flash_stm32_priv {
#define FLASH_STM32_SR SR
#endif


#define FLASH_STM32_PRIV(dev) ((struct flash_stm32_priv *)((dev)->data))
#define FLASH_STM32_REGS(dev) (FLASH_STM32_PRIV(dev)->regs)


/* Redefinitions of flags and masks to harmonize stm32 series: */
#if defined(CONFIG_SOC_SERIES_STM32U5X)
#define FLASH_STM32_NSLOCK FLASH_NSCR_LOCK
Expand Down Expand Up @@ -329,13 +329,13 @@ int flash_stm32_block_erase_loop(const struct device *dev,

int flash_stm32_wait_flash_idle(const struct device *dev);

int flash_stm32_option_bytes_lock(const struct device *dev, bool enable);

uint32_t flash_stm32_option_bytes_read(const struct device *dev);

int flash_stm32_option_bytes_write(const struct device *dev, uint32_t mask,
uint32_t value);

int flash_stm32_cr_lock(const struct device *dev, bool enable);

#ifdef CONFIG_SOC_SERIES_STM32WBX
int flash_stm32_check_status(const struct device *dev);
#endif /* CONFIG_SOC_SERIES_STM32WBX */
Expand Down
76 changes: 76 additions & 0 deletions drivers/flash/flash_stm32_ex_op.c
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Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,82 @@

LOG_MODULE_REGISTER(flash_stm32_ex_op, CONFIG_FLASH_LOG_LEVEL);

int flash_stm32_option_bytes_lock(const struct device *dev, bool enable)
{
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);

#if defined(FLASH_OPTCR_OPTLOCK) /* F2, F4, F7 or H7 */
if (enable) {
regs->OPTCR |= FLASH_OPTCR_OPTLOCK;
} else if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) {
regs->OPTKEYR = FLASH_OPT_KEY1;
regs->OPTKEYR = FLASH_OPT_KEY2;
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@etienne-lms etienne-lms Apr 30, 2025

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Is this missing the H7RSX case?

#ifdef CONFIG_SOC_SERIES_STM32H7RSX
		regs->OPTKEYR = FLASH_OPTKEY1;
		regs->OPTKEYR = FLASH_OPTKEY2;
#else

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@FRASTM FRASTM Apr 30, 2025

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yes, added in the flash_stm32.h file

}
#else
int rc;

/* Unlock CR/PECR/NSCR register if needed. */
if (!enable) {
rc = flash_stm32_cr_lock(dev, false);
if (rc) {
return rc;
}
}

#if defined(FLASH_CR_OPTWRE) /* F0, F1 and F3 */
if (enable) {
regs->CR &= ~FLASH_CR_OPTWRE;
} else if (!(regs->CR & FLASH_CR_OPTWRE)) {
regs->OPTKEYR = FLASH_OPTKEY1;
regs->OPTKEYR = FLASH_OPTKEY2;
}
#elif defined(FLASH_CR_OPTLOCK) /* G0, G4, L4, WB and WL */
if (enable) {
regs->CR |= FLASH_CR_OPTLOCK;
} else if (regs->CR & FLASH_CR_OPTLOCK) {
regs->OPTKEYR = FLASH_OPTKEY1;
regs->OPTKEYR = FLASH_OPTKEY2;
}
#elif defined(FLASH_PECR_OPTLOCK) /* L0 and L1 */
if (enable) {
regs->PECR |= FLASH_PECR_OPTLOCK;
} else if (regs->PECR & FLASH_PECR_OPTLOCK) {
regs->OPTKEYR = FLASH_OPTKEY1;
regs->OPTKEYR = FLASH_OPTKEY2;
}
#elif defined(FLASH_NSCR_OPTLOCK) /* L5 and U5 */
if (enable) {
regs->NSCR |= FLASH_NSCR_OPTLOCK;
} else if (regs->NSCR & FLASH_NSCR_OPTLOCK) {
regs->OPTKEYR = FLASH_OPTKEY1;
regs->OPTKEYR = FLASH_OPTKEY2;
}
#elif defined(FLASH_NSCR1_OPTLOCK) /* WBA */
if (enable) {
regs->NSCR1 |= FLASH_NSCR1_OPTLOCK;
} else if (regs->NSCR1 & FLASH_NSCR1_OPTLOCK) {
regs->OPTKEYR = FLASH_OPTKEY1;
regs->OPTKEYR = FLASH_OPTKEY2;
}
#endif
/* Lock CR/PECR/NSCR register if needed. */
if (enable) {
rc = flash_stm32_cr_lock(dev, true);
if (rc) {
return rc;
}
}
#endif

if (enable) {
LOG_DBG("Option bytes locked");
} else {
LOG_DBG("Option bytes unlocked");
}

return 0;
}

#if defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
int flash_stm32_ex_op_sector_wp(const struct device *dev, const uintptr_t in,
void *out)
Expand Down
25 changes: 0 additions & 25 deletions drivers/flash/flash_stm32h7x.c
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Original file line number Diff line number Diff line change
Expand Up @@ -309,31 +309,6 @@ int flash_stm32_option_bytes_disable(const struct device *dev)
}
#endif /* CONFIG_FLASH_STM32_BLOCK_REGISTERS */

int flash_stm32_option_bytes_lock(const struct device *dev, bool enable)
{
FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);

if (enable) {
regs->OPTCR |= FLASH_OPTCR_OPTLOCK;
} else if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) {
#ifdef CONFIG_SOC_SERIES_STM32H7RSX
regs->OPTKEYR = FLASH_OPTKEY1;
regs->OPTKEYR = FLASH_OPTKEY2;
#else
regs->OPTKEYR = FLASH_OPT_KEY1;
regs->OPTKEYR = FLASH_OPT_KEY2;
#endif /* CONFIG_SOC_SERIES_STM32H7RSX */
}

if (enable) {
LOG_DBG("Option bytes locked");
} else {
LOG_DBG("Option bytes unlocked");
}

return 0;
}

bool flash_stm32_valid_range(const struct device *dev, off_t offset, uint32_t len, bool write)
{
#if defined(DUAL_BANK)
Expand Down