arch/arm: New arch_switch() based context layer for Cortex M

arch/Kconfig

@@ -1031,7 +1031,7 @@ config FPU
 
 config FPU_SHARING
 	bool "FPU register sharing"
-	depends on FPU && MULTITHREADING
+	depends on FPU
 	help
 	  This option enables preservation of the hardware floating point registers
 	  across context switches to allow multiple threads to perform concurrent

arch/arm/core/Kconfig

@@ -6,11 +6,11 @@
 config CPU_CORTEX_M
 	bool
 	select CPU_CORTEX
-	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
+	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN if !USE_SWITCH
 	select HAS_CMSIS_CORE
 	select HAS_FLASH_LOAD_OFFSET
 	select ARCH_HAS_SINGLE_THREAD_SUPPORT
-	select ARCH_HAS_THREAD_ABORT
+	select ARCH_HAS_THREAD_ABORT if  !USE_SWITCH
 	select ARCH_HAS_TRUSTED_EXECUTION if ARM_TRUSTZONE_M
 	select ARCH_HAS_STACK_PROTECTION if (ARM_MPU && !ARMV6_M_ARMV8_M_BASELINE) || CPU_CORTEX_M_HAS_SPLIM
 	select ARCH_HAS_USERSPACE if ARM_MPU

arch/arm/core/cortex_m/CMakeLists.txt

@@ -20,21 +20,22 @@ elseif(CONFIG_ARMV8_1_M_PACBTI_NONE)
 endif()
 
 zephyr_library_sources(
-  exc_exit.c
   fault.c
   fault_s.S
   fpu.c
   reset.S
   scb.c
-  thread_abort.c
   vector_table.S
-  swap_helper.S
+  svc.S
   irq_manage.c
   prep_c.c
   thread.c
   cpu_idle.c
   )
 
+zephyr_library_sources_ifdef(CONFIG_USE_SWITCH arm-m-switch.c)
+zephyr_library_sources_ifndef(CONFIG_USE_SWITCH exc_exit.c thread_abort.c swap_helper.S)
+
 zephyr_library_sources_ifndef(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER irq_init.c)
 zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.c)
 zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c)

arch/arm/core/cortex_m/Kconfig

@@ -106,6 +106,9 @@ config CPU_CORTEX_M7
 
 if CPU_CORTEX_M
 
+config USE_SWITCH
+	default y if USE_SWITCH_SUPPORTED && !ARM_NONSECURE_FIRMWARE
+
 config CPU_CORTEX_M_HAS_SYSTICK
 	bool
 	help
@@ -226,6 +229,7 @@ config ARMV7_M_ARMV8_M_MAINLINE
 	select CPU_CORTEX_M_HAS_VTOR
 	select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
 	select CPU_CORTEX_M_HAS_SYSTICK
+	select USE_SWITCH_SUPPORTED
 	help
 	  This option signifies the use of an ARMv7-M processor
 	  implementation, or the use of a backwards-compatible
@@ -555,6 +559,15 @@ config CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE
 
 endif # CORTEX_M_NULL_POINTER_EXCEPTION
 
+config ARM_GCC_FP_WORKAROUND
+	bool "GCC/gas frame pointer workaround"
+	help
+	  Enables a two-instruction workaround for a GNU toolchain
+	  buglet in arch_switch() when the kernel must unavoidably be
+	  compiled with -fno-omit-frame-pointer.  Most code doesn't
+	  want this, but in at least one case it's necessary.  See
+	  comment in arm-m-switch.h
+
 rsource "tz/Kconfig"
 
 endif # CPU_CORTEX_M