cmake: linker: dont place device tree memories at absolute addresses

[RobinKastberg]

In CMAKE_LINKER_GENERATOR linker scripts, avoid placing the device tree memories at an absolute address. This avoids placing both .rom_start AND SSRAM1 at the same address on mps2/an521/cpu0.

This seems fine according to ld (since one placement is empty) but causes a currently non-suppressable error in IAR linker.

I am a bit unclear about the reason for this construction.
Is it to be able to do attribute(section("SSRAM1")) after having configured the device tree, then that is very handy. But doesn't really require specific ADDRESS.

Or are there use cases I am not thinking about here?

[tejlmand]

I am a bit unclear about the reason for this construction. Is it to be able to do attribute(section("SSRAM1")) after having configured the device tree, then that is very handy. But doesn't really require specific ADDRESS.

Or are there use cases I am not thinking about here?

The reason for this is when devicetree defines memory regions, for example like DTCM in this case:

zephyr/boards/arm/mps3/mps3_corstone300_an547.dts

Lines 76 to 80 in 95c1c85

	dtcm: dtcm@30000000 { /* alias @ 0x20000000 */
	compatible = "zephyr,memory-region";
	reg = <0x30000000 DT_SIZE_K(512)>;
	zephyr,memory-region = "DTCM";
	};

then the linker generator should create a corresponding memory region and section.
For example for ld scripts like this:

MEMORY                                                                                              
{                                                                                                   
  ...
  DTCM (rw) : ORIGIN = (0x30000000), LENGTH = (0x80000)                                             
  ...
}

DTCM 0x30000000 (NOLOAD) :                                                                          
{                                                                                                   
  __DTCM_start = .;                                                                                 
  *(DTCM)                                                                                           
  *("DTCM.*")                                                                                       
  __DTCM_end = .;                                                                                   
} > DTCM                                                                   

and there the address of 0x30000000 should of course correspond to the address defined in devicetree.

By using the memory region node from devicetree we remove the requirement that the user must duplicate this information in CMake.

[tejlmand]

In CMAKE_LINKER_GENERATOR linker scripts, avoid placing the device tree memories at an absolute address. This avoids placing both .rom_start AND SSRAM1 at the same address on mps2/an521/cpu0.

I see how this could be a problem to some linkers, and is probably not noticed until now because as you mention then ld has no problems with such colliding addresses.

I looked a bit at the ld generator, and it seems the ld generator is actually using the value from the memory region (zephyr_linker_dts_memory()) and not the value given fetched in zephyr_linker_dts_section(), which means that the change in this PR doesn't seem to affect the ld generator.
I need to check the scatter file generator before a potential approval.

[RobinKastberg]

By using the memory region node from devicetree we remove the requirement that the user must duplicate this information in CMake.

This was something like I expected. But I still don't see anyone using the actual sections.. And this usage is not easy to search for.
To follow your example above, dtcm sections are still specified in arm/linker.cmake and it doesn't seem like anyone is placing stuff in sections with the automatically generated name DTCM/ITCM/SSRAM1 etc.

[tejlmand]

To follow your example above, dtcm sections are still specified in arm/linker.cmake and it doesn't seem like anyone is placing stuff in sections with the automatically generated name DTCM/ITCM/SSRAM1 etc.

That could be because not all code placement has been updated.
For example, DTCM region was originally added here: #17123

And the creation of memory regions and sections based on devicetree was added here: #43603
See also #42008 for additional info.

The ld-templates still creates the same memory regions and sections as we should be doing in the CMake linker:

zephyr/include/zephyr/arch/arm/cortex_m/scripts/linker.ld

Line 93 in 4bb5ffd

LINKER_DT_REGIONS()

zephyr/include/zephyr/arch/arm/cortex_m/scripts/linker.ld

Lines 406 to 407 in 4bb5ffd

	/* Sections generated from 'zephyr,memory-region' nodes */
	LINKER_DT_SECTIONS()

@carlocaione do you have any additional input regarding this topic ?

[RobinKastberg]

yup, matching the ld skeletons is the best way.
This is an interesting discussion but have we actually uncovered anything stopping this change?

[tejlmand]

This is an interesting discussion but have we actually uncovered anything stopping this change?

ah right, this doesn't change the creation of the memory regions, only adjustment of the output section.
Guess I got myself a bit side-tracked when explaining the devicetree to linker memory creation 😅

[nhutnguyenkc]

Looks good. We will try IAR on Renesas boards soon.

[RobinKastberg]

@nhutnguyenkc

Looks good. We will try IAR on Renesas boards soon.

Ah good!

We have a known issue that CMAKE_LINKER_GENERATOR is not in sync with LD skeleton for renesas boards (option bytes).
I have been meaning to look into it but maybe you can do it?

e.g. for ek_ra4e2

Error[Lc036]: no block or place matches the pattern "ro data section .id_code in bsp_rom_registers.c.o"
Error[Lc036]: no block or place matches the pattern "ro data section .option_setting_bps_sec0 in bsp_rom_registers.c.o"
Error[Lc036]: no block or place matches the pattern "ro data section .option_setting_ofs0 in bsp_rom_registers.c.o"
Error[Lc036]: no block or place matches the pattern "ro data section .option_setting_ofs1_sec in bsp_rom_registers.c.o"
Error[Lc036]: no block or place matches the pattern "ro data section .option_setting_pbps_sec0 in bsp_rom_registers.c.o"
Error[Lc036]: no block or place matches the pattern "ro data section .option_setting_sas in bsp_rom_registers.c.o"

[nhutnguyenkc]

@RobinKastberg , it seems now is the right time to try IAR :)
Could you please share us the build command to reproduce these errors?
I think @thenguyenyf can help you with that. We can find each other on Discord for further discussion.