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  • Implemented async flash erase and writes using the STM32 hal HAL_FLASHEx_Erase_IT() and HAL_FLASH_Program_IT() functions with their associated interrupt handler.
  • I only implemented this for the h7, l4, and f4 stm32 families because that is the hardware I had available to test on.
  • Async flash transactions can be enabled using the FLASH_STM32_ASYNC config option.
  • Async transactions are implemented using a semaphore which blocks while waiting for the flash IRQ to indicate the end of a flash transaction. This allows other threads to take action while flash erase and write actions are taking place.

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Hello @jpowen898, and thank you very much for your first pull request to the Zephyr project!
Our Continuous Integration pipeline will execute a series of checks on your Pull Request commit messages and code, and you are expected to address any failures by updating the PR. Please take a look at our commit message guidelines to find out how to format your commit messages, and at our contribution workflow to understand how to update your Pull Request. If you haven't already, please make sure to review the project's Contributor Expectations and update (by amending and force-pushing the commits) your pull request if necessary.
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@jpowen898 jpowen898 force-pushed the main branch 2 times, most recently from c34e153 to ae67109 Compare July 16, 2025 14:49
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@nordicjm Thanks for the feedback. I made all the requested changes, let me know if there is anything else.

@zephyrbot zephyrbot requested a review from etienne-lms July 17, 2025 16:05
@jpowen898 jpowen898 force-pushed the main branch 2 times, most recently from 9129568 to b5d3812 Compare July 17, 2025 16:13
@jpowen898 jpowen898 requested a review from nordicjm July 17, 2025 16:16
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I just did some testing with this on the stm32h743 and it is failing to erase the correct sectors because of this issue #93714 where the flash size is being calculated incorrectly (4MB when it should be 2MB) and caused the get_sector() to return the wrong bank and sector numbers. It looks like there is a PR open to fix it already #93739.

@zephyrbot zephyrbot added the Release Notes To be mentioned in the release notes label Jul 28, 2025
@zephyrbot zephyrbot requested review from cfriedt and jhedberg July 28, 2025 17:31
@jpowen898 jpowen898 force-pushed the main branch 3 times, most recently from caed1f4 to 7157818 Compare July 31, 2025 15:11
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@etienne-lms etienne-lms left a comment

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Check also the few comments posted by CI compliance checks bot.

Added optional use of the stm32 hal async flash write and erase
capabilities on the l4, f4, and h7 soc families. It is implemented
using semaphores to allow for other threads to take action during
the erase/write actions. This feature is disabled by default and
can be optionally enabled using the FLASH_STM32_ASYNC config option.

Signed-off-by: Parker Owen <[email protected]>
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sonarqubecloud bot commented Sep 5, 2025

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Minor issues, otherwise LGTM.

#else /* CONFIG_FLASH_STM32_ASYNC */

int rc;
uint32_t tmp;
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tmp is already defined at function entry.

#endif /* CONTROL_DCACHE */

return rc;
#endif /* !CONFIG_FLASH_STM32_ASYNC */
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Prefer:

Suggested change
#endif /* !CONFIG_FLASH_STM32_ASYNC */
#endif /* CONFIG_FLASH_STM32_ASYNC */

Ditto at a few other places.

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7 participants