soc: raspberrypi: rp2350: support AMP builds

boards/raspberrypi/common/rpi_pico-led.dtsi

@@ -9,6 +9,7 @@
 	leds {
 		compatible = "gpio-leds";
 		led0: led_0 {
+			status = "disabled";
 			gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
 			label = "LED";
 		};

boards/raspberrypi/rpi_pico/rpi_pico.dts

@@ -8,3 +8,7 @@
 
 #include "rpi_pico-common.dtsi"
 #include "../common/rpi_pico-led.dtsi"
+
+&led0 {
+	status = "okay";
+};

boards/raspberrypi/rpi_pico2/Kconfig.rpi_pico2

@@ -4,3 +4,5 @@
 
 config BOARD_RPI_PICO2
 	select SOC_RP2350A_M33 if BOARD_RPI_PICO2_RP2350A_M33 || BOARD_RPI_PICO2_RP2350A_M33_W
+	select SOC_RP2350A_M33_CPU0 if BOARD_RPI_PICO2_RP2350A_M33_CPU0
+	select SOC_RP2350A_M33_CPU1 if BOARD_RPI_PICO2_RP2350A_M33_CPU1

boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi

@@ -12,19 +12,18 @@
 #include "rpi_pico2-pinctrl.dtsi"
 #include "../common/rpi_pico-led.dtsi"
 
-/ {
-	chosen {
-		zephyr,sram = &sram0;
-		zephyr,flash = &flash0;
-		zephyr,flash-controller = &qmi;
-		zephyr,console = &uart0;
-		zephyr,shell-uart = &uart0;
-	};
-
-	aliases {
-		watchdog0 = &wdt0;
-	};
+/*
+ * We need to be careful about shared definitions in this
+ * device tree. Zephyr will run start up code on peripherals
+ * that are present here - meaning it will get run twice.
+ * Best case, this is a bit wasteful as the bus accesses are
+ * arbitrated. Worst case, the peripherals are left in an
+ * unknown state based on the order of access.
+ * Bacause of this, we mark all peripherals as "reserved"
+ * and will only enable them in the core-specific device trees
+ */
 
+/ {
 	pico_header: connector {
 		compatible = "raspberrypi,pico-header";
 		#gpio-cells = <2>;
@@ -61,61 +60,64 @@
 
 &flash0 {
 	reg = <0x10000000 DT_SIZE_M(4)>;
+	status = "reserved";
 };
 
 &uart0 {
 	current-speed = <115200>;
-	status = "okay";
+	status = "reserved";
 	pinctrl-0 = <&uart0_default>;
 	pinctrl-names = "default";
 };
 
 gpio0_lo: &gpio0 {
-	status = "okay";
+	status = "reserved";
 };
 
 &spi0 {
 	clock-frequency = <DT_FREQ_M(8)>;
 	pinctrl-0 = <&spi0_default>;
 	pinctrl-names = "default";
+	status = "reserved";
 };
 
 &i2c0 {
 	clock-frequency = <I2C_BITRATE_STANDARD>;
 	pinctrl-0 = <&i2c0_default>;
 	pinctrl-names = "default";
-	status = "okay";
+	status = "reserved";
 };
 
 &i2c1 {
 	clock-frequency = <I2C_BITRATE_STANDARD>;
 	pinctrl-0 = <&i2c1_default>;
 	pinctrl-names = "default";
-	status = "okay";
+	status = "reserved";
 };
 
 &adc {
 	pinctrl-0 = <&adc_default>;
 	pinctrl-names = "default";
-	status = "okay";
+	status = "reserved";
 };
 
 &pwm {
 	pinctrl-0 = <&pwm_ch4b_default>;
 	pinctrl-names = "default";
 	divider-int-0 = <255>;
+	status = "reserved";
 };
 
 &timer0 {
-	status = "okay";
+	status = "reserved";
 };
 
 &wdt0 {
-	status = "okay";
+	status = "reserved";
 };
 
 zephyr_udc0: &usbd {
-	status = "okay";
+	status = "reserved";
 };
 
 pico_serial: &uart0 {};

boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.dts

@@ -20,3 +20,64 @@
  * implemented) Hazard3 cores.
  */
 #include "rpi_pico2.dtsi"
+
+/ {
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+
+	aliases {
+		watchdog0 = &wdt0;
+	};
+};
+
+&flash0 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+gpio0_lo: &gpio0 {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&adc {
+	status = "okay";
+};
+
+&pwm {
+	status = "okay";
+};
+
+&timer0 {
+	status = "okay";
+};
+
+&wdt0 {
+	status = "okay";
+};
+
+zephyr_udc0: &usbd {
+	status = "okay";
+};
+
+&led0 {
+	status = "okay";
+};

boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_cpu0.dts

@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2024 Andrew Featherstone
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+/* The build system assumes that there's a cpucluster-specific file.
+ *
+ * This file provides composition of the device tree:
+ * 1. The common features of the SoC
+ * 2. Core-specific configuration.
+ * 3. Board-specific configuration.
+ */
+#include <raspberrypi/rpi_pico/rp2350a.dtsi>
+#include <raspberrypi/rpi_pico/m33.dtsi>
+
+/* there's nothing specific to the Cortex-M33 cores vs the (not yet
+ * implemented) Hazard3 cores.
+ */
+#include "rpi_pico2.dtsi"
+#include "rpi_pico2_split.dtsi"
+
+/delete-node/ &cpu1;
+
+/ {
+	chosen {
+		zephyr,sram = &sram0_cpu0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+
+	aliases {
+		watchdog0 = &wdt0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+gpio0_lo: &gpio0 {
+	status = "okay";
+};
+
+&led0 {
+	status = "okay";
+};
+
+&flash0 {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&adc {
+	status = "okay";
+};
+
+&pwm {
+	status = "okay";
+};
+
+&timer0 {
+	status = "okay";
+};
+
+&wdt0 {
+	status = "okay";
+};

boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_cpu0.yaml

@@ -0,0 +1,16 @@
+identifier: rpi_pico2/rp2350a/m33_cpu0
+name: Raspberry Pi Pico 2 (Cortex-M33 CPU0)
+type: mcu
+arch: arm
+flash: 4096
+ram: 256
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - clock
+  - counter
+  - hwinfo
+  - i2c
+  - pwm
+  - uart

boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_cpu0_defconfig

@@ -0,0 +1,13 @@
+# This configuration is orthogonal to whether the Cortex-M33 or Hazard3 cores
+# are in use, but Zephyr does not support providing a qualifier-agnostic
+# _defconfig file.
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_BUILD_OUTPUT_UF2=y
+CONFIG_CLOCK_CONTROL=y
+CONFIG_CONSOLE=y
+CONFIG_GPIO=y
+CONFIG_RESET=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_USE_DT_CODE_PARTITION=y

boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_cpu1.dts

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2024 Andrew Featherstone
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+/* The build system assumes that there's a cpucluster-specific file.
+ *
+ * This file provides composition of the device tree:
+ * 1. The common features of the SoC
+ * 2. Core-specific configuration.
+ * 3. Board-specific configuration.
+ */
+#include <raspberrypi/rpi_pico/rp2350a.dtsi>
+#include <raspberrypi/rpi_pico/m33.dtsi>
+
+/* there's nothing specific to the Cortex-M33 cores vs the (not yet
+ * implemented) Hazard3 cores.
+ */
+#include "rpi_pico2.dtsi"
+#include "rpi_pico2_split.dtsi"
+
+/delete-node/ &cpu0;
+
+/ {
+	chosen {
+		zephyr,sram = &sram0_cpu1;
+		// Flash is only assigned to CPU0, CPU1 must
+		// execute from RAM to avoid access conflicts
+		// You can add a code-partition
+		// Then add image-source to the &cpu1_launcher on cpu0
+		// zephyr,code-partition = &cpu1_slot0_partition;
+	};
+};
+
+zephyr_udc0: &usbd {
+	status = "okay";
+};

boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_cpu1.yaml

@@ -0,0 +1,13 @@
+identifier: rpi_pico2/rp2350a/m33_cpu1
+name: Raspberry Pi Pico 2 (Cortex-M33 CPU1)
+type: mcu
+arch: arm
+flash: 0
+ram: 256
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - hwinfo
+  - uart
+  - usbd

boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33_cpu1_defconfig

@@ -0,0 +1,13 @@
+# This configuration is orthogonal to whether the Cortex-M33 or Hazard3 cores
+# are in use, but Zephyr does not support providing a qualifier-agnostic
+# _defconfig file.
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_BUILD_OUTPUT_UF2=y
+CONFIG_CLOCK_CONTROL=y
+CONFIG_CONSOLE=y
+CONFIG_RESET=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_USE_DT_CODE_PARTITION=y
+CONFIG_XIP=n