arch: riscv: introduce common layer for RISC-V custom CSRs #93697

jimmyzhe · 2025-07-25T06:01:18Z

This PR is inspired by #91940.

RISC-V allows custom CSR implementation. Some SoCs from different SoC vendors may share the same core or the same custom CSR definitions and drivers.
For example, Andes AE350, Telink TLSR9518, and Egis ET171 all support Andes-specific CSRs.

This PR introduces ~~soc/common/riscv-custom~~ zephyr/arch/riscv/custom, which centralizes support for custom CSRs, allowing code reuse across SoCs that come from different vendors.

Currently supported these custom CSR:

Andes
Nuclei
OpenHWGroup CVA6
OpenISA RI5CY
OpenISA Zero-riscy
T-Head

nordicjm · 2025-07-25T08:03:11Z

soc/common/riscv-custom/andes/Kconfig

+config CPU_HAS_ANDES_EXECIT
+	bool
+	help
+		The AndesCore supports EXEC.IT instruction.


help text indent is 1x tab followed by 2x spaces

Fixed it, thanks.

nordicjm · 2025-07-25T08:03:30Z

soc/common/riscv-custom/andes/Kconfig

+		The AndesCore supports EXEC.IT instruction.
+
+config RISCV_CUSTOM_CSR_ANDES_EXECIT
+	bool "Andes V5 EXEC.IT extension"


why do any of these have prompts?

This remains the original design from andestech/ae350 and telink/tlsr/tlsr951x.
The SoC selects Andes extensions through CPU_HAS_ANDES_XXX, while applications can decide whether to use them or not.

For example, a SoC may support the Andes HWDSP or PFT extension, but if the application doesn’t use them, the user can disable these features via these options.

jimmyzhe · 2025-07-25T09:14:51Z

Removed old Kconfig option in adp_xc7k_ae350_clic_defconfig.

Hi @kevinwang821020 , there are some issues with the dma_andes_atcdmac300 driver check or the adp_xc7k_ae350.conf in tests/drivers/dma.
Could you help take a look?

npitre · 2025-07-25T18:56:13Z

I wonder if zephyr/socscommon/ is the proper location for this...

Either this is vendor specific in which case this should be in
zephyr/soc/<vendor>/ or this is more architectural in which case it
might rather be in zephyr/arch/riscv/custom/.

kevinwang821020 · 2025-07-28T05:10:57Z

Removed old Kconfig option in adp_xc7k_ae350_clic_defconfig.

Hi @kevinwang821020 , there are some issues with the dma_andes_atcdmac300 driver check or the adp_xc7k_ae350.conf in tests/drivers/dma. Could you help take a look?

Based on the current atcdmac driver codebase, it need to do the cache operations(CONFIG_CACHE_MANAGEMENT) for chain_block when DCACHE is enabled, even CONFIG_NOCACHE_MEMORY is enable.

I have already prepared a previous PR ( PR #85272 ) which includes fixing this problem.

jimmyzhe · 2025-07-28T09:13:59Z

Either this is vendor specific in which case this should be in zephyr/soc/<vendor>/ or this is more architectural in which case it might rather be in zephyr/arch/riscv/custom/.

Right, custom CSR is RISC-V feature, I think placing these in zephyr/arch/riscv/custom is more appropriate and simple to reuse.

Moved the custom CSR common code to zephyr/arch/riscv/custom and also fixed the help text indentation in zephyr/arch/riscv/custom/andes/Kconfig.

jimmyzhe · 2025-10-08T10:44:33Z

Rebased to main and enabled Andes custom CSR support for Egis ET171.

Andes specific toolchain options currently in ‎soc/egis/et171/CMakeLists.txt will be moved to cmake/compiler/andes in #96833.

ping @jackylee-go.

ycsin · 2025-10-08T14:44:46Z

arch/riscv/custom/Kconfig

+
+if DT_HAS_ANDESTECH_ANDESCORE_V5_ENABLED
+
+rsource "andes/Kconfig"


This line is ahead of its time - the file is only available in the next commit?

Fixed it, thanks.

ycsin

LGTM otherwise

RISC-V allows custom CSR implementation. Some SoCs from different vendors may share the same core or the same custom CSR definitions and drivers. This patch introduces 'arch/riscv/custom', which centralizes support for custom CSRs, allowing code reuse across SoCs that come from different vendors. Currently supported thess custom CSR: 1. Andes 2. Nuclei 3. OpenHWGroup CVA6 4. OpenISA RI5CY 5. OpenISA Zero-riscy 6. T-Head Xuantie Signed-off-by: Jimmy Zheng <[email protected]>

jimmyzhe · 2025-10-09T10:47:39Z

I add arch/riscv/custom for RISC-V custom CSR originally, while I think it also fit for RISC-V custom instruction.

Move arch/riscv/xuantie to arch/riscv/custom/thead.
And seperate T-Head Xuantie into

T-Head Extension: ‎arch/riscv/custom/thead/Kconfig
Xuantie Core: ‎arch/riscv/custom/thead/Kconfig.core

nordicjm · 2025-10-13T08:34:05Z

soc/andestech/ae350/CMakeLists.txt

-if(CONFIG_SOC_SERIES_ANDES_AE350)
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
+  if(CONFIG_RISCV_CUSTOM_CSR_ANDES_NEXECIT)
+    zephyr_ld_options(-Wl,--mnexecitop)


no place for these in this file

nordicjm · 2025-10-13T08:34:12Z

soc/egis/et171/CMakeLists.txt

+
+# Note: AndeStar V5 DSP needs custom Andes V5 toolchain
+if(CONFIG_RISCV_CUSTOM_CSR_ANDES_HWDSP)
+  zephyr_cc_option(-mext-dsp)


Rework Andes-specific CSR to use RISC-V custom CSR common code. Move these stuff to 'arch/riscv/custom/andes': 1. Rename 'soc_v5.h' to 'andes_csr.h' for CSR definitions. 2. Replace '_start' with '__reset' hook for low-level CSR initialization. 3. Move CSR context to common macro '__custom_csr_save/restore_context'. 4. Move 'EXECIT' CSR support to common code. 5. Move PMA CSR driver to common code. 6. Use RISC-V common linker.ld instead of SoC-specific linker.ld. Signed-off-by: Jimmy Zheng <[email protected]>

TLSR951x also supports Andes extended CSR. Reworks the following CSR handling to use the RISC-V custom CSR common code: 1. Use common macros for HWDSP CSR context save/restore. 2. Use common macros for PFT CSR context save/restore. 3. Use common low-level CSR initialization via __reset hook. Signed-off-by: Jimmy Zheng <[email protected]>

Egis ET171 implements Andes custom CSRs. Enable the following features: 1. Low level initialization of Andes CSRs 2. HWDSP and PowerBrake extensions with context save/restore 3. EXEC.IT extension Signed-off-by: Jimmy Zheng <[email protected]>

GD32VF103 uses Nuclei-specific CSR. Move 'nuclei_csr.h' to 'arch/riscv/custom' to allow reuse across SoCs with the same Nuclei core. Signed-off-by: Jimmy Zheng <[email protected]>

CVA6 supports custom CSR. Move 'cva6.h' to 'arch/riscv/custom/cva6_csr.h', allowing other SoCs using the CVA6 core to reuse the same CSR definitions. Signed-off-by: Jimmy Zheng <[email protected]>

Update OpenISA RI5CY and Zero-RISCY CSR handling to use RISC-V custom CSR common code. Move these stuff to 'arch/riscv/custom/openisa': 1. Rename 'soc_ri5cy.h' to 'ri5cy_csr.h' for CSR definitions. 2. Rename 'soc_zero_riscy.h' to 'zero_riscy_csr.h' for CSR definitions. 3. Move CSR context to common macro '__custom_csr_save/restore_context'. 4. Move compiler option '-march=rv32imcxpulpv2' to common code. Signed-off-by: Jimmy Zheng <[email protected]>

Move Xuantie supprot from arch/riscv/core/xuantie to the custom common layer arch/riscv/custom/thead, with the following changes: 1. Rename Kconfig name CACHE_XTHEADCMO -> RISCV_CUSTOM_CSR_THEAD_CMO 2. Split the original arch/riscv/core/xuantie/Kconfig to a. arch/riscv/custom/thead/Kconfig: for T-Head extension b. arch/riscv/custom/thead/Kconfig.core: for T-Head CPU series (e.g. Xuantie E907) 3. Move cache line size defaults to SoC devicetree Signed-off-by: Jimmy Zheng <[email protected]>

sonarqubecloud · 2025-10-13T09:40:01Z

Quality Gate passed

Issues
7 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

jimmyzhe · 2025-10-13T09:55:43Z

Remove the newly add Andes specific toolchain options in soc/egis/et171 and soc/andestech/ae350.
I will add these in the Andes toolchain file in #96833.

zephyrbot added area: Cache area: RISCV RISCV Architecture (32-bit & 64-bit) platform: Andes Technology platform: GD32 GigaDevice labels Jul 25, 2025

zephyrbot requested review from VynDragon, cameled, carlocaione, edersondisouza, fkokosinski, katsuster, kevinwang821020, kgugala, masz-nordic, mgielda, nandojve, npitre, soburi, tgorochowik and ycsin July 25, 2025 06:02

zephyrbot assigned fkokosinski, kgugala and tgorochowik Jul 25, 2025

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jimmyzhe force-pushed the riscv_custom_csr branch from dfc6db4 to 9ed0e2a Compare July 25, 2025 08:33

kevinwang821020 mentioned this pull request Jul 28, 2025

drivers: dma: atcdmac300: Upgrade atcdmac driver to support series device #85272

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jimmyzhe force-pushed the riscv_custom_csr branch from 9ed0e2a to 3f7bb7c Compare July 28, 2025 08:32

jimmyzhe force-pushed the riscv_custom_csr branch from 0ebe37a to 6cf34e3 Compare October 8, 2025 10:56

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jimmyzhe force-pushed the riscv_custom_csr branch from 6cf34e3 to d8f2bd1 Compare October 9, 2025 09:24

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zephyrbot added area: Devicetree Bindings platform: Bouffalo Lab labels Oct 9, 2025

jimmyzhe force-pushed the riscv_custom_csr branch from 759a141 to 3e90903 Compare October 9, 2025 09:35

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Support heterogeneous uArches features #97130

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jimmyzhe added 7 commits October 13, 2025 17:09

arch: riscv: : custom: add Nuclei CSR support

8c62f34

GD32VF103 uses Nuclei-specific CSR. Move 'nuclei_csr.h' to 'arch/riscv/custom' to allow reuse across SoCs with the same Nuclei core. Signed-off-by: Jimmy Zheng <[email protected]>

arch: riscv: custom: add OpenHW Group CVA6 CSR support

352a844

CVA6 supports custom CSR. Move 'cva6.h' to 'arch/riscv/custom/cva6_csr.h', allowing other SoCs using the CVA6 core to reuse the same CSR definitions. Signed-off-by: Jimmy Zheng <[email protected]>

jimmyzhe dismissed fkokosinski’s stale review via de100db October 13, 2025 09:14

jimmyzhe force-pushed the riscv_custom_csr branch from 3e90903 to de100db Compare October 13, 2025 09:14

nordicjm approved these changes Oct 13, 2025

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fkokosinski approved these changes Oct 13, 2025

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ycsin approved these changes Oct 13, 2025

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cfriedt merged commit 7edb310 into zephyrproject-rtos:main Oct 13, 2025
33 checks passed


		if DT_HAS_ANDESTECH_ANDESCORE_V5_ENABLED

		rsource "andes/Kconfig"

arch: riscv: introduce common layer for RISC-V custom CSRs #93697

arch: riscv: introduce common layer for RISC-V custom CSRs #93697

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