drivers: sdhc: litex: add support for litesdcard

arch/riscv/custom/CMakeLists.txt

@@ -6,4 +6,5 @@ add_subdirectory_ifdef(CONFIG_DT_HAS_OPENHWGROUP_CVA6_ENABLED openhwgroup/cva6)
 add_subdirectory_ifdef(CONFIG_DT_HAS_NUCLEI_BUMBLEBEE_ENABLED nuclei)
 add_subdirectory_ifdef(CONFIG_DT_HAS_OPENISA_RI5CY_ENABLED openisa/ri5cy)
 add_subdirectory_ifdef(CONFIG_DT_HAS_OPENISA_ZERO_RI5CY_ENABLED openisa/zero_riscy)
+add_subdirectory_ifdef(CONFIG_DT_HAS_SPINALHDL_VEXRISCV_ENABLED vexriscv)
 add_subdirectory_ifdef(CONFIG_DT_HAS_XUANTIE_E907_ENABLED thead)

arch/riscv/custom/Kconfig

@@ -7,6 +7,12 @@ rsource "andes/Kconfig"
 
 endif # DT_HAS_ANDESTECH_ANDESCORE_V5_ENABLED
 
+if DT_HAS_SPINALHDL_VEXRISCV_ENABLED
+
+rsource "vexriscv/Kconfig"
+
+endif # DT_HAS_SPINALHDL_VEXRISCV_ENABLED
+
 if DT_HAS_XUANTIE_E907_ENABLED
 
 rsource "thead/Kconfig"

arch/riscv/custom/vexriscv/CMakeLists.txt

@@ -0,0 +1,4 @@
+# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_sources_ifdef(CONFIG_RISCV_CUSTOM_CSR_VEXRISCV_CACHE cache_vexriscv.c)

arch/riscv/custom/vexriscv/Kconfig

@@ -0,0 +1,9 @@
+# SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+config RISCV_CUSTOM_CSR_VEXRISCV_CACHE
+	bool
+	default y
+	depends on ARCH_CACHE
+	help
+	  This option enables cache support for VexRiscv family of CPUs.

arch/riscv/custom/vexriscv/cache_vexriscv.c

@@ -0,0 +1,116 @@
+/*
+ * SPDX-FileCopyrightText: Copyright The Zephyr Project Contributors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/cache.h>
+
+#ifdef CONFIG_DCACHE
+void arch_dcache_enable(void)
+{
+	/* Nothing */
+}
+
+void arch_dcache_disable(void)
+{
+	/* Nothing */
+}
+
+int arch_dcache_invd_all(void)
+{
+	__asm__ volatile(".insn 0x500F\n");
+
+	return 0;
+}
+
+int arch_dcache_invd_range(void *addr, size_t size)
+{
+	__asm__ volatile(
+		"mv a0, %1\n"
+		"j 2f\n"
+		"3:\n"
+		".insn 0x5500F\n" /* 0x500f | (a0 << 15) */
+		"add a0, a0, %0\n"
+		"2:\n"
+		"bltu a0, %2, 3b\n"
+		: : "r"(CONFIG_DCACHE_LINE_SIZE),
+			"r"((unsigned int)(addr) & ~((CONFIG_DCACHE_LINE_SIZE) - 1UL)),
+			"r"((unsigned int)(addr) + (size))
+		: "a0");
+
+	return 0;
+}
+
+
+int arch_dcache_flush_all(void)
+{
+	/* VexRiscv cache is write-through */
+	return 0;
+}
+
+int arch_dcache_flush_range(void *addr __unused, size_t size __unused)
+{
+	return 0;
+}
+
+int arch_dcache_flush_and_invd_all(void)
+{
+	return arch_dcache_invd_all();
+}
+
+int arch_dcache_flush_and_invd_range(void *addr, size_t size)
+{
+	return arch_dcache_invd_range(addr, size);
+}
+#endif /* CONFIG_DCACHE */
+
+#ifdef CONFIG_ICACHE
+void arch_icache_enable(void)
+{
+	/* Nothing */
+}
+
+void arch_icache_disable(void)
+{
+	/* Nothing */
+}
+
+int arch_icache_flush_all(void)
+{
+	__asm__ volatile("fence.i\n");
+
+	return 0;
+}
+
+int arch_icache_invd_all(void)
+{
+	return arch_icache_flush_all();
+}
+
+int arch_icache_invd_range(void *addr_in __unused, size_t size __unused)
+{
+	return arch_icache_flush_all();
+}
+
+int arch_icache_flush_and_invd_all(void)
+{
+	return arch_icache_flush_all();
+}
+
+int arch_icache_flush_range(void *addr __unused, size_t size __unused)
+{
+	return arch_icache_flush_all();
+}
+
+int arch_icache_flush_and_invd_range(void *addr __unused, size_t size __unused)
+{
+	return arch_icache_flush_all();
+}
+#endif /* CONFIG_ICACHE */
+
+void arch_cache_init(void)
+{
+	/* Nothing */
+}

boards/enjoydigital/litex_vexriscv/Kconfig.defconfig

@@ -3,11 +3,10 @@
 
 if BOARD_LITEX_VEXRISCV
 
-if NETWORKING
-
-config NET_L2_ETHERNET
+configdefault NET_L2_ETHERNET
 	default y
 
-endif # NETWORKING
+configdefault SDHC_LITEX_LITESDCARD_NO_COHERENT_DMA
+	default y
 
 endif # BOARD_LITEX_VEXRISCV

boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts

@@ -26,6 +26,80 @@
 		device_type = "memory";
 		reg = <0x40000000 0x10000000>;
 	};
+
+	soc {
+		sdhc0: sdhc@e000e800 {
+			compatible = "litex,litesdcard-sdhc";
+			interrupt-parent = <&intc0>;
+			reg = <0xe000e800 0x4>,
+				<0xe000e804 0x4>,
+				<0xe000e808 0x4>,
+				<0xe000e80c 0x4>,
+				<0xe000e810 0x4>,
+				<0xe000e814 0x4>,
+				<0xe000e818 0x4>,
+				<0xe000e81c 0x4>,
+				<0xe000e820 0x4>,
+				<0xe000e824 0x4>,
+				<0xe000e828 0x10>,
+				<0xe000e838 0x4>,
+				<0xe000e83c 0x4>,
+				<0xe000e840 0x4>,
+				<0xe000e844 0x4>,
+				<0xe000e848 0x8>,
+				<0xe000e850 0x4>,
+				<0xe000e854 0x4>,
+				<0xe000e858 0x4>,
+				<0xe000e85c 0x4>,
+				<0xe000e860 0x4>,
+				<0xe000e864 0x8>,
+				<0xe000e86c 0x4>,
+				<0xe000e870 0x4>,
+				<0xe000e874 0x4>,
+				<0xe000e878 0x4>,
+				<0xe000e87c 0x4>,
+				<0xe000e880 0x4>,
+				<0xe000e884 0x4>,
+				<0xe000e888 0x4>;
+			reg-names = "phy_card_detect",
+				"phy_clocker_divider",
+				"phy_init_initialize",
+				"phy_cmdr_timeout",
+				"phy_dataw_status",
+				"phy_datar_timeout",
+				"phy_settings",
+				"core_cmd_argument",
+				"core_cmd_command",
+				"core_cmd_send",
+				"core_cmd_response",
+				"core_cmd_event",
+				"core_data_event",
+				"core_block_length",
+				"core_block_count",
+				"block2mem_dma_base",
+				"block2mem_dma_length",
+				"block2mem_dma_enable",
+				"block2mem_dma_done",
+				"block2mem_dma_loop",
+				"block2mem_dma_offset",
+				"mem2block_dma_base",
+				"mem2block_dma_length",
+				"mem2block_dma_enable",
+				"mem2block_dma_done",
+				"mem2block_dma_loop",
+				"mem2block_dma_offset",
+				"ev_status",
+				"ev_pending",
+				"ev_enable";
+			interrupts = <5 1>;
+			status = "okay";
+			mmc {
+				compatible = "zephyr,sdmmc-disk";
+				status = "okay";
+				disk-name = "SD";
+			};
+		};
+	};
 };
 
 &ctrl0 {

boards/enjoydigital/litex_vexriscv/litex_vexriscv.yaml

@@ -15,6 +15,7 @@ supported:
   - gpio
   - uart
   - spi
+  - sdhc
   - i2s
   - i2c
   - watchdog

drivers/sdhc/CMakeLists.txt

@@ -14,6 +14,7 @@ zephyr_library_sources_ifdef(CONFIG_SDHC_INFINEON_CAT1 ifx_cat1_sdio.c)
 zephyr_library_sources_ifdef(CONFIG_CDNS_SDHC sdhc_cdns_ll.c sdhc_cdns.c)
 zephyr_library_sources_ifdef(CONFIG_SDHC_ESP32 sdhc_esp32.c)
 zephyr_library_sources_ifdef(CONFIG_SDHC_RENESAS_RA sdhc_renesas_ra.c)
+zephyr_library_sources_ifdef(CONFIG_SDHC_LITEX_LITESDCARD sdhc_litex_litesdcard.c)
 zephyr_library_sources_ifdef(CONFIG_SDHC_MAX32 sdhc_max32.c)
 zephyr_library_sources_ifdef(CONFIG_SDHC_AMBIQ sdhc_ambiq.c)
 zephyr_library_sources_ifdef(CONFIG_XLNX_SDHC xlnx_sdhc.c)

drivers/sdhc/Kconfig

@@ -19,6 +19,7 @@ source "drivers/sdhc/Kconfig.intel"
 source "drivers/sdhc/Kconfig.sdhc_cdns"
 source "drivers/sdhc/Kconfig.esp32"
 source "drivers/sdhc/Kconfig.renesas_ra"
+source "drivers/sdhc/Kconfig.litex"
 source "drivers/sdhc/Kconfig.max32"
 source "drivers/sdhc/Kconfig.ambiq"
 source "drivers/sdhc/Kconfig.xlnx"

drivers/sdhc/Kconfig.litex

@@ -0,0 +1,26 @@
+# Copyright The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+config SDHC_LITEX_LITESDCARD
+	bool "LiteX LiteSDCard SDHC driver"
+	default y
+	depends on DT_HAS_LITEX_LITESDCARD_SDHC_ENABLED
+	select SDHC_SUPPORTS_NATIVE_MODE
+	help
+	  sdhc driver for LiteX LiteSDCard.
+
+if SDHC_LITEX_LITESDCARD
+
+configdefault SDHC_BUFFER_ALIGNMENT
+	default 4
+
+config SDHC_LITEX_LITESDCARD_NO_COHERENT_DMA
+	bool "No coherent DMA bus, need cache management"
+	select CACHE_MANAGEMENT
+	depends on DCACHE
+	help
+	  This needs to be enabled if the LiteSDCard Module is not connected
+	  to a coherent DMA bus, meaning that the cache needs to be managed
+	  before and after DMA operations.
+
+endif # SDHC_LITEX_LITESDCARD