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NXP imx93 cm33 enable userspace mode #93906

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NXP imx93 cm33 enable userspace mode #93906

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59cea26
soc: nxp: imx93: m33: enable trdc setting across all execution modes
yongxu-wang15 Jul 31, 2025
ef231b1
modules: hal_nxp: set sentinel device driver state as on
yongxu-wang15 Jul 31, 2025
fe04062
modules: hal_nxp: add trdc_1 driver component
yongxu-wang15 Jul 31, 2025
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1 change: 1 addition & 0 deletions modules/hal_nxp/mcux/mcux-sdk-ng/device/device.cmake
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Original file line number Diff line number Diff line change
Expand Up @@ -68,6 +68,7 @@ endif()
if(NOT CONFIG_CPU_CORTEX_A)
set(CONFIG_MCUX_COMPONENT_driver.reset ON)
set(CONFIG_MCUX_COMPONENT_driver.memory ON)
set(CONFIG_MCUX_COMPONENT_driver.sentinel ON)
endif()

# Include fsl_dsp.c for ARM domains (applicable to i.MX RTxxx devices)
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1 change: 1 addition & 0 deletions modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake
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Expand Up @@ -132,6 +132,7 @@ set_variable_ifdef(CONFIG_DAI_NXP_ESAI CONFIG_MCUX_COMPONENT_driver.esa
set_variable_ifdef(CONFIG_MCUX_LPCMP CONFIG_MCUX_COMPONENT_driver.lpcmp)
set_variable_ifdef(CONFIG_NXP_RF_IMU CONFIG_MCUX_COMPONENT_driver.imu)
set_variable_ifdef(CONFIG_TRDC_MCUX_TRDC CONFIG_MCUX_COMPONENT_driver.trdc)
set_variable_ifdef(CONFIG_TRDC_MCUX_TRDC_1 CONFIG_MCUX_COMPONENT_driver.trdc_1)
set_variable_ifdef(CONFIG_S3MU_MCUX_S3MU CONFIG_MCUX_COMPONENT_driver.s3mu)
set_variable_ifdef(CONFIG_DAI_NXP_MICFIL CONFIG_MCUX_COMPONENT_driver.pdm)
set_variable_ifdef(CONFIG_PINCTRL_NXP_PORT CONFIG_MCUX_COMPONENT_driver.port)
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3 changes: 3 additions & 0 deletions soc/nxp/imx/imx9/imx93/Kconfig.defconfig.mimx93.m33
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Expand Up @@ -17,4 +17,7 @@ config NUM_IRQS
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 200000000

config TRDC_MCUX_TRDC_1
default y
bool "Use TRDC_1 MCUX Driver"
endif
52 changes: 52 additions & 0 deletions soc/nxp/imx/imx9/imx93/m33/soc.c
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Expand Up @@ -8,14 +8,66 @@
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#ifdef CONFIG_USERSPACE
#include <fsl_trdc.h>
#include <fsl_sentinel.h>
#endif

#ifdef CONFIG_SOC_EARLY_INIT_HOOK
#ifdef CONFIG_USERSPACE
void soc_init_trdc(void)
{
uint32_t i, j;

/* Release TRDC(transfer owner of TRDC from s400 to m33) */
SENTINEL_ReleaseRDC(TRDC_TYPE);

/* Enable all access modes for MBC and MRC in all running mode */
trdc_hardware_config_t hwConfig;
trdc_memory_access_control_config_t memAccessConfig;

(void)memset(&memAccessConfig, 0, sizeof(memAccessConfig));
memAccessConfig.nonsecureUsrX = 1U;
memAccessConfig.nonsecureUsrW = 1U;
memAccessConfig.nonsecureUsrR = 1U;
memAccessConfig.nonsecurePrivX = 1U;
memAccessConfig.nonsecurePrivW = 1U;
memAccessConfig.nonsecurePrivR = 1U;
memAccessConfig.secureUsrX = 1U;
memAccessConfig.secureUsrW = 1U;
memAccessConfig.secureUsrR = 1U;
memAccessConfig.securePrivX = 1U;
memAccessConfig.securePrivW = 1U;
memAccessConfig.securePrivR = 1U;

TRDC_GetHardwareConfig(TRDC1, &hwConfig);
for (i = 0U; i < hwConfig.mrcNumber; i++) {
for (j = 0U; j < 8; j++) {
TRDC_MrcSetMemoryAccessConfig(TRDC1, &memAccessConfig, i, j);
}
}

for (i = 0U; i < hwConfig.mbcNumber; i++) {
for (j = 0U; j < 8; j++) {
TRDC_MbcSetMemoryAccessConfig(TRDC1, &memAccessConfig, i, j);
}
}
}
#endif

void soc_early_init_hook(void)
{
/* Configure secure access to pin registers */
GPIO1->PCNS = 0x0;
GPIO2->PCNS = 0x0;
GPIO3->PCNS = 0x0;
GPIO4->PCNS = 0x0;

#ifdef CONFIG_USERSPACE
/* atf configure basic trdc setting about m33 core
* init trdc for all running mode when enabled user space context
*/
soc_init_trdc();
#endif
}
#endif
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