This saves the EXCCAUSE and EXCVADDR into BSA during exception.
These will then be used during exception handling. The reason
for doing this instead of reading from both registers during
exception handing is that another exception will override
the value in these register (e.g. DTLB miss). When returning to
the previous exception handler, these register no longer
contains the original exception cause and address. We need to
save it so that we are actually handling the orignal exception.

Coredump also now uses the EXCCAUSE and EXCVADDR from BSA
instead of reading the registers.

Signed-off-by: Daniel Leung <[email protected]>

This adds a function to handle DTLB multihit exception when
userspace is enabled, as this exception may be raised due to
the same page being able to accessed by both kernel and user
threads. The auto-refill DTLBs may contain entries for same
page, one for kernel and one for user under some situations.
We need to invalidate those existing DTLB entries so that
hardware can reload from the page table.

This is an alternative to the kconfig invalidating DTLBs on
every swap: CONFIG_XTENSA_MMU_FLUSH_AUTOREFILL_DTLBS_ON_SWAP.
Although this does not have extra processing per context
switching, exception handling itself has a high cost. So
care needs to be taken on whether to enable that kconfig.

Signed-off-by: Daniel Leung <[email protected]>

This moves the block of FPU and HIFI registers in the Base Save
Area (BSA), used during interrupts and exceptions, to the end of
the block. This is done to minimize code usage in the vector
text section. During interrupt entrance, the code stores a small
set of registers first before jumping to the long handler. When
the offset to these registers from the beginning of BSA is small
enough, the compiler will emit S32I.N instead of S32I. This
saves us one byte per store (2 vs 3 bytes). This is mainly done
to avoid overflowing the vector text area.

Signed-off-by: Daniel Leung <[email protected]>

xtensa_asm2_s.h is not exactly a C header. Rename it to
xtensa_asm2.inc.S to clearly state that it is has assembly
code in it as its main purpose is to declare assembly macros.
This is being done to keep checkpatch.pl from treating it as
C file and complaining about non-C syntax.

Signed-off-by: Daniel Leung <[email protected]>

This is simply done to conserve code space in the vector text
areas. These vector text areas are very small and we should
only put code that is absolutely necessary for interrupt and
exception entrance. The saving of PS into the thread struct
can be deferred a bit. So do that.

Signed-off-by: Daniel Leung <[email protected]>

The assert error messages when l2_page_table_map() fails are not
correct. It returns false when it cannot allocate new L2 table,
and it is not able the address having already mapped. So correct
the error message.

Signed-off-by: Daniel Leung <[email protected]>

In functions which manipulate both L1 and L2 tables, make
the variable names obvious by prefixing them with l1_ or l2_.
This is mainly done to avoid confusion when reading through
those functions.

Signed-off-by: Daniel Leung <[email protected]>

arch_mem_map() takes in some flags to describe the to-be mapped
memory regions' permissions and cache status. When the flags are
translated, they become attributes in PTEs. So for functions
being called by arch_mem_map() and beyond, rename flags to
attrs to better describe its purpose.

Signed-off-by: Daniel Leung <[email protected]>

The priv_stack_ptr for reading and writing tests was not set
correctly on Xtensa, and was always 0. Test would pass since
the NULL page should always generate access faults on most
Xtensa platforms. However, those tests are supposed to test
reading and writing to the privilege stack. So fix that by
populating the priv_stack_ptr correctly.

Signed-off-by: Daniel Leung <[email protected]>

This adds a few tests to test switching between threads where
they are under different memory domains. This is mainly to test
if permissions are set correctly during context switch.

By default the new tests are disabled and must be explicitly
enabled. This is due to some architectures requiring some config
changes (for example, x86 needing more reserved memory domains,
and ARM64 needing more translation tables). To avoid causing
mass CI failures, only enable platforms that have been tested,
for now.

Signed-off-by: Daniel Leung <[email protected]>