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xtensa: userspace: handle DTLB multihit and incorrect load/store ring exceptions #93947

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xtensa: userspace: handle DTLB multihit and incorrect load/store ring exceptions #93947

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f04208d
xtensa: fatal: use named macros for PS register bits...
dcpleung Jul 24, 2025
55274d2
xtensa: mmu: properly restore PTE attributes via reset_region()
dcpleung Aug 12, 2025
7a94c84
xtensa: save EXCCAUSE/EXCVADDR in BSA during exception
dcpleung Jul 30, 2025
9ed581d
xtensa: userspace: handle load/store ring exception
dcpleung Jul 29, 2025
40da30f
xtensa: userspace: handle DTLB multihit exception
dcpleung Jul 29, 2025
7928fef
xtensa: move saved FPU and HIFI registers to end of BSA
dcpleung Aug 4, 2025
082c5dc
xtensa: rename xtensa_asm2_s.h to xtensa_asm2.inc.S
dcpleung Oct 8, 2025
580d6ec
xtensa: userspace: save PS to thread struct later
dcpleung Aug 4, 2025
02ff0c6
xtensa: mmu: fix __arch_mem_map assert message
dcpleung Aug 8, 2025
b9443f8
xtensa: mmu: cosmetic changes to page table variable names
dcpleung Aug 8, 2025
81eb9fe
xtensa: mmu/ptables: rename flags to attrs under arch_mem_map()
dcpleung Aug 11, 2025
3512d6f
tests: mem_protect/userspace: fix privilege stack ptr for Xtensa
dcpleung Jul 24, 2025
d8b8697
tests: mem_protect/userspace: add thread switching tests
dcpleung Jul 24, 2025
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5 changes: 2 additions & 3 deletions arch/xtensa/core/coredump.c
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Original file line number Diff line number Diff line change
Expand Up @@ -135,8 +135,6 @@ void arch_coredump_info_dump(const struct arch_esf *esf)
xtensa_coredump_fault_sp = (uint32_t)esf;
#endif

__asm__ volatile("rsr.exccause %0" : "=r"(arch_blk.r.exccause));

_xtensa_irq_stack_frame_raw_t *frame = (void *)esf;
_xtensa_irq_bsa_t *bsa = frame->ptr_to_bsa;
uintptr_t num_high_regs;
Expand All @@ -150,7 +148,7 @@ void arch_coredump_info_dump(const struct arch_esf *esf)
regs_blk_remaining = (int)num_high_regs / 4;

arch_blk.r.pc = bsa->pc;
__asm__ volatile("rsr.excvaddr %0" : "=r"(arch_blk.r.excvaddr));
arch_blk.r.excvaddr = bsa->excvaddr;
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ah, so was this the reason for wrong EXCVADDR values in my dumps? nice!

arch_blk.r.ps = bsa->ps;
#if XCHAL_HAVE_S32C1I
arch_blk.r.scompare1 = bsa->scompare1;
Expand All @@ -160,6 +158,7 @@ void arch_coredump_info_dump(const struct arch_esf *esf)
arch_blk.r.a1 = (uint32_t)((char *)bsa) + sizeof(*bsa);
arch_blk.r.a2 = bsa->a2;
arch_blk.r.a3 = bsa->a3;
arch_blk.r.exccause = bsa->exccause;
if (regs_blk_remaining > 0) {
regs_blk_remaining--;

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2 changes: 1 addition & 1 deletion arch/xtensa/core/gen_zsr.py
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Expand Up @@ -31,7 +31,7 @@ def parse_args():

NEEDED = ["A0SAVE", "CPU"]
if args.mmu:
NEEDED += ["DBLEXC", "DEPC_SAVE", "EXCCAUSE_SAVE"]
NEEDED += ["DBLEXC", "DEPC_SAVE"]
if args.flush_reg:
NEEDED += ["FLUSH"]

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1 change: 1 addition & 0 deletions arch/xtensa/core/offsets/offsets.c
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Expand Up @@ -22,6 +22,7 @@ GEN_OFFSET_SYM(_xtensa_irq_bsa_t, a2);
GEN_OFFSET_SYM(_xtensa_irq_bsa_t, a3);

GEN_OFFSET_SYM(_xtensa_irq_bsa_t, exccause);
GEN_OFFSET_SYM(_xtensa_irq_bsa_t, excvaddr);
GEN_OFFSET_SYM(_xtensa_irq_bsa_t, pc);
GEN_OFFSET_SYM(_xtensa_irq_bsa_t, ps);
GEN_OFFSET_SYM(_xtensa_irq_bsa_t, sar);
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