board: arm64: Add suport for ROC-RK3588

boards/firefly/roc_rk3588/Kconfig.roc_rk3588

@@ -0,0 +1,5 @@
+# Copyright The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ROC_RK3588
+	select SOC_RK3588

boards/firefly/roc_rk3588/board.yml

@@ -0,0 +1,8 @@
+board:
+  name: roc_rk3588
+  full_name: ROC-RK3588 (Quad-core Cortex-A55)
+  vendor: firefly
+  socs:
+  - name: rk3588
+    variants:
+    - name: smp

boards/firefly/roc_rk3588/doc/index.rst

@@ -0,0 +1,137 @@
+.. zephyr:board:: roc_rk3588
+
+Overview
+********
+
+The ROC-RK3588 is an Octa-Core 64-Bit Mini Computer powered by Rockchip RK3588, which supports up to 32GB RAM.
+It features M.2 PCIe3.0 interface for NVMe SSD expansion and provides rich interfaces including HDMI 2.1, DP1.4.
+Supporting WiFi 6 wireless transmission and Gigabit Ethernet, it enables high-speed network connectivity.
+
+RK3588 octa-core 64-bit processor (4×Cortex-A76+4×Cortex-A55), with 8nm lithography process,
+has frequency up to 2.4GHz. Integrated with ARM Mali-G610 MP4 quad-core GPU and built-in AI accelerator NPU,
+it provides 6Tops computing power. Zephyr OS is ported to run on it.
+
+
+- Board features:
+
+  - RAM: Up to 32GB LPDDR4/LPDDR4x/LPDDR5
+  - Storage:
+
+    - Up to 128GB eMMC
+    - M.2 PCIe3.0 NVMe SSD (2242/2260/2280)
+    - TF-Card Slot
+  - Wireless:
+
+    - Supports WiFi 6 (802.11 a/b/g/n/ac/ax)
+    - Supports BT 5.0
+  - Display:
+
+    - HDMI 2.1 (8K@60fps)
+    - HDMI 2.0 (4K@60fps)
+    - DP 1.4 (8K@30fps)
+  - USB:
+
+    - Two USB 3.0
+    - One USB 2.0
+    - One USB-C (USB3.0 OTG / DP1.4)
+  - Network:
+
+    - 1x 1000Mbps Ethernet (RJ45)
+  - Debug:
+
+    - UART debug ports for board
+  - Other:
+
+    - NPU with 6 TOPS computing power
+    - ARM Mali-G610 MP4 quad-core GPU
+    - Support OpenGL ES3.2/OpenCL 2.2/Vulkan1.1
+
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Devices
+========
+System Clock
+------------
+
+This board configuration uses a system clock frequency of 24 MHz.
+Cortex-A76 cores run up to 2.4 GHz and Cortex-A55 cores run up to 1.8 GHz.
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+CPU's UART2.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Use U-Boot to load the zephyr.bin to the memory and kick it:
+
+.. code-block:: console
+
+    tftp 0x50000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x50000000
+
+Use this configuration to run basic Zephyr applications and kernel tests,
+for example, with the :zephyr:code-sample:`synchronization` sample:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: roc_rk3588
+   :goals: run
+
+This will build an image with the synchronization sample app, boot it and
+display the following ram console output:
+
+.. code-block:: console
+
+    ***  Booting Zephyr OS build v4.1.0-2356-gfe6366b8045a  ***
+    thread_a: Hello World from cpu 0 on roc_rk3588!
+    thread_b: Hello World from cpu 0 on roc_rk3588!
+    thread_a: Hello World from cpu 0 on roc_rk3588!
+    thread_b: Hello World from cpu 0 on roc_rk3588!
+
+
+``roc_rk3588//smp`` support, use this configuration to run Zephyr smp applications and subsys tests,
+for example, with the :zephyr:code-sample:`synchronization` sample:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: roc_rk3588//smp
+   :goals: run
+
+This will build an image with the shell_module sample app, boot it and
+display the following ram console output:
+
+.. code-block:: console
+
+    ***  Booting Zephyr OS build v4.1.0-2356-gfe6366b8045a  ***
+    I/TC: Secondary CPU 1 initializing
+    I/TC: Secondary CPU 1 switching to normal world boot
+    Secondary CPU core 1 (MPID:0x100) is up
+    I/TC: Secondary CPU 2 initializing
+    I/TC: Secondary CPU 2 switching to normal world boot
+    Secondary CPU core 2 (MPID:0x200) is up
+    I/TC: Secondary CPU 3 initializing
+    I/TC: Secondary CPU 3 switching to normal world boot
+    Secondary CPU core 3 (MPID:0x300) is up
+    thread_a: Hello World from cpu 0 on roc_rk3588!
+    thread_b: Hello World from cpu 1 on roc_rk3588!
+    thread_a: Hello World from cpu 0 on roc_rk3588!
+    thread_b: Hello World from cpu 1 on roc_rk3588!
+
+References
+==========
+
+More information can refer to Firefly official website:
+`Firefly website`_.
+
+.. _Firefly website:
+   https://en.t-firefly.com/product/industry/rocrk3588pc.html?theme=pc

boards/firefly/roc_rk3588/roc_rk3588.dts

@@ -0,0 +1,36 @@
+/*
+ * Copyright The Zephyr Project Contributors
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <arm64/rockchip/rk3588.dtsi>
+#include <common/mem.h>
+
+/ {
+	model = "Firefly ROC-RK3588";
+	compatible = "rockchip,rk3588";
+
+	chosen {
+		zephyr,console = &uart2;
+		zephyr,shell-uart = &uart2;
+		zephyr,sram = &dram;
+	};
+
+	dram: memory@50000000 {
+		compatible = "mmio-sram";
+		device_type = "memory";
+		reg = <0x50000000 DT_SIZE_M(1)>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+	current-speed = <1500000>;
+};
+
+&uart3 {
+	status = "disabled";
+	current-speed = <115200>;
+};

boards/firefly/roc_rk3588/roc_rk3588.yaml

@@ -0,0 +1,12 @@
+identifier: roc_rk3588
+name: Rockchip ROC RK3588
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+ram: 1024
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/firefly/roc_rk3588/roc_rk3588_defconfig

@@ -0,0 +1,20 @@
+# Copyright The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+# Platform Configuration
+CONFIG_ARM_ARCH_TIMER=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# ARMv8 NS world with cache management
+CONFIG_ARMV8_A_NS=y
+CONFIG_CACHE_MANAGEMENT=y
+
+CONFIG_TICKLESS_KERNEL=y

boards/firefly/roc_rk3588/roc_rk3588_smp.dts

@@ -0,0 +1,6 @@
+/*
+ * Copyright The Zephyr Project Contributors
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "roc_rk3588.dts"

boards/firefly/roc_rk3588/roc_rk3588_smp.yaml

@@ -0,0 +1,14 @@
+identifier: roc_rk3568_pc/rk3568/smp
+name: Rockchip ROC RK3568 PC SMP
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+ram: 1024
+supported:
+  - smp
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/firefly/roc_rk3588/roc_rk3588_smp_defconfig

@@ -0,0 +1,30 @@
+# Copyright The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+# Platform Configuration
+CONFIG_ARM_ARCH_TIMER=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# ARMv8 NS world with cache management
+CONFIG_ARMV8_A_NS=y
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_DCACHE=y
+
+CONFIG_TICKLESS_KERNEL=y
+
+# SMP support
+CONFIG_SMP=y
+CONFIG_MP_MAX_NUM_CPUS=4
+CONFIG_MAX_THREAD_BYTES=4
+
+# PSCI support
+CONFIG_PM_CPU_OPS=y
+CONFIG_PM_CPU_OPS_PSCI=y

dts/arm64/rockchip/rk3588.dtsi

@@ -0,0 +1,98 @@
+/*
+ * Copyright 2020 NXP
+ * Copyright 2022 HNU-ESNL
+ * Copyright 2022 openEuler SIG-Zephyr
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm64/armv8-a.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	compatible = "rockchip,rk3588";
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			enable-method = "psci";
+			clock-frequency = <24000000>;
+			reg = <0x000>;
+		};
+
+		cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			enable-method = "psci";
+			reg = <0x100>;
+		};
+
+		cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			enable-method = "psci";
+			reg = <0x200>;
+
+		};
+
+		cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			enable-method = "psci";
+			reg = <0x300>;
+		};
+	};
+
+	gic: interrupt-controller@fe600000 {
+		#address-cells = <1>;
+		compatible = "arm,gic-v3","arm,gic";
+		#interrupt-cells = <4>;
+		interrupt-controller;
+
+		reg = <0xfe600000 0x10000>, /* GICD */
+		      <0xfe680000 0x100000>; /* GICR */
+		status = "okay";
+	};
+
+	psci {
+		compatible = "arm,psci-0.2", "arm,psci";
+		method = "smc";
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+	};
+
+	uart2: serial@feb50000 {
+		compatible = "rockchip,rk3588-uart", "ns16550";
+		reg = <0xfeb50000 0x100>;
+		interrupts = <GIC_SPI 333 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+		clock-frequency = <12000000>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart3: serial@feb60000 {
+		compatible = "rockchip,rk3588-uart", "ns16550";
+		reg = <0xfeb60000 0x100>;
+		interrupts = <GIC_SPI 334 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+		clock-frequency = <24000000>;
+		reg-shift = <2>;
+		status = "disabled";
+	};	
+};

soc/rockchip/rk35/CMakeLists.txt

@@ -5,4 +5,6 @@ if(CONFIG_SOC_RK3568)
   add_subdirectory(rk3568)
 elseif(CONFIG_SOC_RK3588S)
   add_subdirectory(rk3588s)
+elseif(CONFIG_SOC_RK3588)
+  add_subdirectory(rk3588)
 endif()

soc/rockchip/rk35/rk3588/CMakeLists.txt

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")