Add STM32U5 support to STM32 MIPI DSI driver #94433
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@@ -26,6 +26,20 @@ | |
| status = "disabled"; | ||
| }; | ||
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| mipi_dsi: dsihost@40016c00 { | ||
| compatible = "st,stm32u5-mipi-dsi", "st,stm32-mipi-dsi"; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
| reg = <0x40016C00 0x1000>; | ||
| clock-names = "dsiclk", "dsisrc", "refclk", "pixelclk"; | ||
| clocks = <&rcc STM32_CLOCK(APB2, 27U)>, | ||
| <&rcc STM32_SRC_DSIPHY DSI_SEL(1)>, | ||
| <&rcc STM32_SRC_HSE NO_SEL>, | ||
| <&rcc STM32_SRC_PLL3_R NO_SEL>; | ||
| resets = <&rctl STM32_RESET(APB2, 27U)>; | ||
| status = "disabled"; | ||
| }; | ||
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| xspi1: spi@420d3400 { | ||
| compatible = "st,stm32-xspi"; | ||
| reg = <0x420d3400 0x400>, | ||
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,132 @@ | ||
| # | ||
| # Copyright (c) 2025 Charles Dias | ||
| # | ||
| # SPDX-License-Identifier: Apache-2.0 | ||
| # | ||
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| description: | | ||
| STM32U5 series MIPI DSI controller. | ||
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| compatible: "st,stm32u5-mipi-dsi" | ||
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| include: | ||
| - name: st,stm32-mipi-dsi.yaml | ||
| property-blocklist: | ||
| - clock-names | ||
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| properties: | ||
| clock-names: | ||
| type: string-array | ||
| required: true | ||
| description: | | ||
| "dsiclk" DSI clock enable. | ||
| "dsisrc" DSI clock source. | ||
| "refclk" External crystal or oscillator clock. | ||
| "pixelclk" LTDC pixel clock. | ||
| "refclk" and "pixelclk" are only used to retrieve the frequency for timing calculation. | ||
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| phy-freq-range: | ||
| required: true | ||
| type: int | ||
| enum: | ||
| - 0x0 | ||
| - 0x1 | ||
| - 0x2 | ||
| - 0x3 | ||
| - 0x4 | ||
| - 0x5 | ||
| - 0x6 | ||
| - 0x7 | ||
| - 0x8 | ||
| description: | | ||
| D-PHY PLL input frequency range. This is used to select the appropriate | ||
| frequency range for the D-PHY PLL operation. | ||
| 0x0 : DSI_DPHY_FRANGE_80MHZ_100MHZ | ||
| 0x1 : DSI_DPHY_FRANGE_100MHZ_120MHZ | ||
| 0x2 : DSI_DPHY_FRANGE_120MHZ_160MHZ | ||
| 0x3 : DSI_DPHY_FRANGE_160MHZ_200MHZ | ||
| 0x4 : DSI_DPHY_FRANGE_200MHZ_240MHZ | ||
| 0x5 : DSI_DPHY_FRANGE_240MHZ_320MHZ | ||
| 0x6 : DSI_DPHY_FRANGE_320MHZ_390MHZ | ||
| 0x7 : DSI_DPHY_FRANGE_390MHZ_450MHZ | ||
| 0x8 : DSI_DPHY_FRANGE_450MHZ_510MHZ | ||
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| phy-low-power-offset: | ||
| required: true | ||
| type: int | ||
| enum: | ||
| - 0x0 | ||
| - 0x1 | ||
| - 0x2 | ||
| - 0x3 | ||
| - 0x4 | ||
| - 0x5 | ||
| - 0x6 | ||
| - 0x7 | ||
| - 0x8 | ||
| - 0x9 | ||
| - 0xA | ||
| - 0xB | ||
| - 0xC | ||
| - 0xD | ||
| - 0xE | ||
| - 0xF | ||
| description: | | ||
| D-PHY low power offset configuration specific to STM32U5 series. | ||
| 0x0 : PHY_LP_OFFSSET_0_CLKP (0 CLKP) | ||
| 0x1 : PHY_LP_OFFSSET_1_CLKP (+1 CLKP) | ||
| 0x2 : PHY_LP_OFFSSET_2_CLKP (+2 CLKP) | ||
| 0x3 : PHY_LP_OFFSSET_3_CLKP (+3 CLKP) | ||
| 0x4 : PHY_LP_OFFSSET_4_CLKP (+4 CLKP) | ||
| 0x5 : PHY_LP_OFFSSET_5_CLKP (+5 CLKP) | ||
| 0x6 : PHY_LP_OFFSSET_6_CLKP (+6 CLKP) | ||
| 0x7 : PHY_LP_OFFSSET_7_CLKP (+7 CLKP) | ||
| 0x8 : PHY_LP_OFFSSET_MINUS_1_CLKP (-1 CLKP) | ||
| 0x9 : PHY_LP_OFFSSET_MINUS_2_CLKP (-2 CLKP) | ||
| 0xA : PHY_LP_OFFSSET_MINUS_3_CLKP (-3 CLKP) | ||
| 0xB : PHY_LP_OFFSSET_MINUS_4_CLKP (-4 CLKP) | ||
| 0xC : PHY_LP_OFFSSET_MINUS_5_CLKP (-5 CLKP) | ||
| 0xD : PHY_LP_OFFSSET_MINUS_6_CLKP (-6 CLKP) | ||
| 0xE : PHY_LP_OFFSSET_MINUS_7_CLKP (-7 CLKP) | ||
| 0xF : PHY_LP_OFFSSET_MINUS_8_CLKP (-8 CLKP) | ||
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| pll-vco-range: | ||
| required: true | ||
| type: int | ||
| enum: | ||
| - 0x0 | ||
| - 0x1 | ||
| description: | | ||
| PLL VCO frequency range configuration for STM32U5 D-PHY. | ||
| 0x0 : DSI_DPHY_VCO_FRANGE_500MHZ_800MHZ | ||
| 0x1 : DSI_DPHY_VCO_FRANGE_800MHZ_1GHZ | ||
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| pll-charge-pump: | ||
| required: true | ||
| type: int | ||
| enum: | ||
| - 0x0 | ||
| - 0x1 | ||
| - 0x2 | ||
| - 0x3 | ||
| description: | | ||
| PLL charge pump configuration for STM32U5 D-PHY. | ||
| Valid values: | ||
| 0x0 : DSI_PLL_CHARGE_PUMP_2000HZ_4400HZ | ||
| 0x1 : DSI_PLL_CHARGE_PUMP_4400HZ_14100HZ | ||
| 0x0 : DSI_PLL_CHARGE_PUMP_14100HZ_30900HZ | ||
| 0x3 : DSI_PLL_CHARGE_PUMP_30900HZ_45700HZ | ||
| 0x2 : DSI_PLL_CHARGE_PUMP_45700HZ_50000HZ | ||
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| pll-tuning: | ||
| required: true | ||
| type: int | ||
| enum: | ||
| - 0x0 | ||
| - 0x1 | ||
| - 0x2 | ||
| description: | | ||
| PLL tuning parameter (loop filter) for STM32U5 D-PHY. | ||
| 0x0 : DSI_PLL_LOOP_FILTER_2000HZ_4400HZ | ||
| 0x1 : DSI_PLL_LOOP_FILTER_4400HZ_30900HZ | ||
| 0x2 : DSI_PLL_LOOP_FILTER_30900HZ_50000HZ |
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@@ -38,6 +38,8 @@ | |
| #define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1) | ||
| #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1) | ||
| #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1) | ||
| /** DSI PHY clock */ | ||
| #define STM32_SRC_DSIPHY (STM32_SRC_PLL3_R + 1) | ||
| /** Clock muxes */ | ||
| /* #define STM32_SRC_ICLK TBD */ | ||
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@@ -89,7 +91,7 @@ | |
| #define SAE_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 11, CCIPR2_REG) | ||
| #define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG) | ||
| #define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR2_REG) | ||
| #define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, CCIPR2_REG) | ||
| #define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 16, CCIPR2_REG) | ||
| #define LTDC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 18, CCIPR2_REG) | ||
| #define OCTOSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG) | ||
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This highlight a change in the way to define pll-odf between U5 and other platforms. Considering that it is defined the same way in the DT yaml, I don't think it should be used differently between the U5 series and other series.
(or it should be highlighted why this is needed, and highlight in the yaml).
Could you share you dts configuration of your mipi-dsi node for this U5 ?
I haven't check the U5 DSI spec, why lane clock freq calculation has to be different between series ?
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Having checked the HAL code, my understanding is that PLLODF can have a value going from 1 to 9 (1 being divide by 1). So This seems to be ok as far as INIT is concerned, however the real divider factor a 1 << ODF
I am actually wondering if the original computation is correct ...
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Hi @avolmat-st. Thanks for your review.
Please, take a look at the dts configuration here #94423
The
lane_clk_khzcalculation described in document AN4860 Rev 4 page 75 is different from what is described in RM0456 Rev 6 page 1782 asPHI. Additionally, this is also aligned with the STM32CudeIDE representation. Please let me know if I understood wrong.AN4860 Rev 4 page 75
RM0456 Rev 6 page 1782
STM32CudeIDE for H7
STM32CudeIDE for U5
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Thanks @CharlesDias for the clarification. I didn't notice that important different. It make senses then.
U5 support is ok I think then. What might have to be reworked is thus more the H7 rather than the U5 in fact since in case of H7, the PLLODF is not really giving the divider factor by the value to be written into the register, which is not the divider factor. But that is not part of this PR.