trusted-firmware-m: Fix sign images to allow FOTA

boards/arm/mps2/Kconfig.defconfig

@@ -46,6 +46,10 @@ choice NULL_POINTER_EXCEPTION_DETECTION
 
 endchoice
 
+# Get flash configuration for NS image from dts flash partition
+config USE_DT_CODE_PARTITION
+	default y if TRUSTED_EXECUTION_NONSECURE
+
 # By default, if we build for a Non-Secure version of the board,
 # force building with TF-M as the Secure Execution Environment.
 config BUILD_WITH_TFM

boards/arm/mps2/mps2_an521_cpu0_ns.dts

@@ -29,7 +29,8 @@
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
 		zephyr,sram = &ram;
-		zephyr,flash = &code;
+		zephyr,flash = &reserved_memory;
+		zephyr,code-partition = &slot0_ns_partition;
 	};
 
 	leds {
@@ -107,19 +108,49 @@
 		reg = <0x80000000 DT_SIZE_M(16)>;
 	};
 
-	reserved-memory {
+	reserved_memory: reserved-memory@0 {
+		compatible = "soc-nv-flash";
+		reg = <0x0 DT_SIZE_M(4)>;
+		erase-block-size = <4096>;
+		write-block-size = <4>;
 		#address-cells = <1>;
 		#size-cells = <1>;
-		ranges;
 
-		/* This code memory region must match what the TF-M
-		 * project has defined for that board - a single image boot is
-		 * assumed. Please see the memory layout in:
-		 *
-		 * https://github.com/zephyrproject-rtos/trusted-firmware-m/blob/master/platform/ext/target/arm/mps2/an521/partition/flash_layout.h
-		 */
-		code: memory@100000 {
-			reg = <0x00100000 DT_SIZE_K(512)>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/* This code memory region must match what the TF-M
+			 * project has defined for that board - the milti image
+			 * boot is used in Zephyr. See memory layout details in:
+			 *
+			 * https://github.com/zephyrproject-rtos/trusted-firmware-m/blob/master/platform/ext/target/arm/mps2/an521/partition/flash_layout.h
+			 */
+			boot_partition: partition@0 {
+				reg = <0x00000000 DT_SIZE_K(512)>;
+				read-only;
+			};
+
+			slot0_partition: partition@80000 {
+				reg = <0x00080000 DT_SIZE_K(512)>;
+			};
+
+			slot0_ns_partition: partition@100000 {
+				reg = <0x00100000 DT_SIZE_K(512)>;
+			};
+
+			slot1_partition: partition@180000 {
+				reg = <0x00180000 DT_SIZE_K(512)>;
+			};
+
+			slot1_ns_partition: partition@200000 {
+				reg = <0x00200000 DT_SIZE_K(512)>;
+			};
+
+			scratch_partition: partition@280000 {
+				reg = <0x00280000 DT_SIZE_K(512)>;
+			};
 		};
 
 		/* This ram memory region's size is chosen to avoid conflict

boards/arm/mps3/Kconfig

@@ -3,7 +3,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_MPS3
-	select QEMU_TARGET if BOARD_MPS3_CORSTONE300_AN547 || BOARD_MPS3_CORSTONE300_AN547_NS
+	select QEMU_TARGET if BOARD_MPS3_CORSTONE300_AN547
 	select TRUSTED_EXECUTION_NONSECURE if BOARD_MPS3_CORSTONE300_AN547_NS || \
 		BOARD_MPS3_CORSTONE300_AN552_NS || BOARD_MPS3_CORSTONE300_FVP_NS || \
 		BOARD_MPS3_CORSTONE310_AN555_NS || BOARD_MPS3_CORSTONE310_FVP_NS

boards/arm/mps3/Kconfig.defconfig

@@ -2,7 +2,16 @@
 # Copyright 2024-2025 Arm Limited and/or its affiliates <[email protected]>
 # SPDX-License-Identifier: Apache-2.0
 
-if BOARD_MPS3_CORSTONE300_AN547 || BOARD_MPS3_CORSTONE300_AN552 || BOARD_MPS3_CORSTONE300_FVP || BOARD_MPS3_CORSTONE310_AN555 || BOARD_MPS3_CORSTONE310_FVP
+if BOARD_MPS3_CORSTONE300_AN547 || \
+	BOARD_MPS3_CORSTONE300_AN547_NS || \
+	BOARD_MPS3_CORSTONE300_AN552 || \
+	BOARD_MPS3_CORSTONE300_AN552_NS || \
+	BOARD_MPS3_CORSTONE300_FVP || \
+	BOARD_MPS3_CORSTONE300_FVP_NS || \
+	BOARD_MPS3_CORSTONE310_AN555 || \
+	BOARD_MPS3_CORSTONE310_AN555_NS || \
+	BOARD_MPS3_CORSTONE310_FVP || \
+	BOARD_MPS3_CORSTONE310_FVP_NS
 
 # MPU-based null-pointer dereferencing detection cannot
 # be applied as the (0x0 - 0x400) is unmapped but QEMU
@@ -12,6 +21,15 @@ choice NULL_POINTER_EXCEPTION_DETECTION
 	default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET
 endchoice
 
+# Get flash configuration for NS image from dts flash partition
+config USE_DT_CODE_PARTITION
+	default y if TRUSTED_EXECUTION_NONSECURE
+
+# By default, if we build for a Non-Secure version of the board,
+# force building with TF-M as the Secure Execution Environment.
+config BUILD_WITH_TFM
+	default y if TRUSTED_EXECUTION_NONSECURE
+
 if SERIAL
 
 config UART_INTERRUPT_DRIVEN

boards/arm/mps3/board.cmake

@@ -12,7 +12,7 @@
 #
 
 
-if(CONFIG_BOARD_MPS3_CORSTONE300_AN547 OR CONFIG_BOARD_MPS3_CORSTONE300_AN547_NS)
+if(CONFIG_BOARD_MPS3_CORSTONE300_AN547)
   set(SUPPORTED_EMU_PLATFORMS qemu)
 
   # QEMU settings

boards/arm/mps3/mps3_common_ns.dtsi

@@ -0,0 +1,49 @@
+/*
+ * Copyright 2025 Leica Geosystem AG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	reserved_memory: reserved-memory@28000000 {
+		compatible = "soc-nv-flash";
+		reg = <0x28000000 DT_SIZE_M(8)>;
+		erase-block-size = <65536>;
+		write-block-size = <4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/* This code memory region must match what the TF-M
+			 * project has defined for that board - the multi image
+			 * boot is used in Zephyr. See memory layout details in:
+			 *
+			 * https://git.trustedfirmware.org/plugins/gitiles/TF-M/trusted-firmware-m.git/+/refs/heads/main/platform/ext/target/arm/mps3/corstone300/common/partition/flash_layout.h
+			 * https://git.trustedfirmware.org/plugins/gitiles/TF-M/trusted-firmware-m.git/+/refs/heads/main/platform/ext/target/arm/mps3/corstone310/common/partition/flash_layout.h
+			 */
+			slot0_partition: partition@0 {
+				reg = <0x00000000 DT_SIZE_K(512)>;
+			};
+
+			slot0_ns_partition: partition@80000 {
+				reg = <0x00080000 DT_SIZE_M(3)>;
+			};
+
+			slot1_partition: partition@380000 {
+				reg = <0x00380000 DT_SIZE_K(512)>;
+			};
+
+			slot1_ns_partition: partition@400000 {
+				reg = <0x00400000 DT_SIZE_M(3)>;
+			};
+
+			scratch_partition: partition@700000 {
+				reg = <0x00700000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};

boards/arm/mps3/mps3_corstone300_an547_ns.dts

@@ -12,6 +12,8 @@
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
 
+#include "mps3_common_ns.dtsi"
+
 / {
 	compatible = "arm,mps3-an547";
 	#address-cells = <1>;
@@ -20,8 +22,9 @@
 	chosen {
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
-		zephyr,sram = &ram;
-		zephyr,flash = &code;
+		zephyr,sram = &isram_ns;
+		zephyr,flash = &reserved_memory;
+		zephyr,code-partition = &slot0_ns_partition;
 	};
 
 	cpus {
@@ -63,30 +66,19 @@
 		zephyr,memory-region = "DTCM";
 	};
 
-	isram: sram@21000000 {
+	/* The ISRAM blocks are used for both S and NS data. The S reserves 128k
+	 * bytes and the remaining can be used by the NS firmware.
+	 */
+	isram_s: secure_data@21000000 {
 		compatible = "zephyr,memory-region", "mmio-sram";
-		reg = <0x21000000 DT_SIZE_M(4)>;
-		zephyr,memory-region = "ISRAM";
+		reg = <0x21000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "ISRAM-Secure";
 	};
 
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		/* The memory regions defined below must match what the TF-M
-		 * project has defined for that board - a single image boot is
-		 * assumed. Please see the memory layout in:
-		 * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone300/common/partition/flash_layout.h
-		 */
-
-		code: memory@28080000 {
-			reg = <0x28080000 DT_SIZE_K(512)>;
-		};
-
-		ram: memory@21020000 {
-			reg = <0x21020000 DT_SIZE_M(2)>;
-		};
+	isram_ns: non_secure_data@21020000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x21020000 (DT_SIZE_M(4) - DT_SIZE_K(128))>;
+		zephyr,memory-region = "ISRAM-Non-Secure";
 	};
 
 	soc {

boards/arm/mps3/mps3_corstone300_an547_ns.yaml

@@ -9,10 +9,8 @@ identifier: mps3/corstone300/an547/ns
 name: Arm MPS3-Corstone300-AN547_ns
 type: mcu
 arch: arm
-ram: 2048
-flash: 512
-simulation:
-  - name: qemu
+ram: 3968
+flash: 3072
 toolchain:
   - gnuarmemb
   - zephyr

boards/arm/mps3/mps3_corstone300_an552_ns.dts

@@ -11,6 +11,8 @@
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
 
+#include "mps3_common_ns.dtsi"
+
 / {
 	compatible = "arm,mps3-an552";
 	#address-cells = <1>;
@@ -19,8 +21,9 @@
 	chosen {
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
-		zephyr,sram = &ram;
-		zephyr,flash = &code;
+		zephyr,sram = &isram_ns;
+		zephyr,flash = &reserved_memory;
+		zephyr,code-partition = &slot0_ns_partition;
 	};
 
 	cpus {
@@ -62,30 +65,19 @@
 		zephyr,memory-region = "DTCM";
 	};
 
-	isram: sram@21000000 {
+	/* The ISRAM blocks are used for both S and NS data. The S reserves 128k
+	 * bytes and the remaining can be used by the NS firmware.
+	 */
+	isram_s: secure_data@21000000 {
 		compatible = "zephyr,memory-region", "mmio-sram";
-		reg = <0x21000000 DT_SIZE_M(2)>;
-		zephyr,memory-region = "ISRAM";
+		reg = <0x21000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "ISRAM-Secure";
 	};
 
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		/* The memory regions defined below must match what the TF-M
-		 * project has defined for that board - a single image boot is
-		 * assumed. Please see the memory layout in:
-		 * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone300/common/partition/flash_layout.h
-		 */
-
-		code: memory@28080000 {
-			reg = <0x28080000 DT_SIZE_K(512)>;
-		};
-
-		ram: memory@21020000 {
-			reg = <0x21020000 DT_SIZE_M(1)>;
-		};
+	isram_ns: non_secure_data@21020000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x21020000 (DT_SIZE_M(2) - DT_SIZE_K(128))>;
+		zephyr,memory-region = "ISRAM-Non-Secure";
 	};
 
 	soc {

boards/arm/mps3/mps3_corstone300_an552_ns.yaml

@@ -5,8 +5,8 @@ identifier: mps3/corstone300/an552/ns
 name: Arm MPS3-Corstone300-AN552_ns
 type: mcu
 arch: arm
-ram: 2048
-flash: 512
+ram: 1920
+flash: 3072
 toolchain:
   - gnuarmemb
   - zephyr

boards/arm/mps3/mps3_corstone300_fvp_ns.dts

@@ -11,6 +11,8 @@
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
 
+#include "mps3_common_ns.dtsi"
+
 / {
 	compatible = "arm,mps3-fvp";
 	#address-cells = <1>;
@@ -19,8 +21,9 @@
 	chosen {
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
-		zephyr,sram = &ram;
-		zephyr,flash = &code;
+		zephyr,sram = &isram_ns;
+		zephyr,flash = &reserved_memory;
+		zephyr,code-partition = &slot0_ns_partition;
 	};
 
 	cpus {
@@ -62,30 +65,19 @@
 		zephyr,memory-region = "DTCM";
 	};
 
-	isram: sram@21000000 {
+	/* The ISRAM blocks are used for both S and NS data. The S reserves 128k
+	 * bytes and the remaining can be used by the NS firmware.
+	 */
+	isram_s: secure_data@21000000 {
 		compatible = "zephyr,memory-region", "mmio-sram";
-		reg = <0x21000000 DT_SIZE_M(2)>;
-		zephyr,memory-region = "ISRAM";
+		reg = <0x21000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "ISRAM-Secure";
 	};
 
-	reserved-memory {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-
-		/* The memory regions defined below must match what the TF-M
-		 * project has defined for that board - a single image boot is
-		 * assumed. Please see the memory layout in:
-		 * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone300/common/partition/flash_layout.h
-		 */
-
-		code: memory@28080000 {
-			reg = <0x28080000 DT_SIZE_K(512)>;
-		};
-
-		ram: memory@21020000 {
-			reg = <0x21020000 DT_SIZE_M(1)>;
-		};
+	isram_ns: non_secure_data@21020000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x21020000 (DT_SIZE_M(2) - DT_SIZE_K(128))>;
+		zephyr,memory-region = "ISRAM-Non-Secure";
 	};
 
 	soc {