driver: inter-processor mailbox for Raspberry Pi Pico #94502
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Hello @r-c-n, and thank you very much for your first pull request to the Zephyr project! |
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platform: Raspberry Pi Pico
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Duplicated ? > #92923 |
No, this is not a dupe. Work of Dan and mine is an IPM subsys driver while this is mailbox. They should probably coexist just like on other platforms like nRF or STM32, and I thought about implementing mbox myself as well once I land the IPM. Wdyt? I will try to review this change when I have time |
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Ugh I wasn't aware of #92923 |
It is targeting the same device with a different API. Later I will provide examples, but e.g. ESP32 implements both options to be chosen by the application. So this PR is likely useful |
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| LOG_DBG("CPU %d: send IP data: %d", sio_hw->cpuid, *((int *)msg->data)); | ||
| sio_hw->fifo_wr = *((uint32_t *)(msg->data)); |
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I'd probably send the channel number here. Most consumers expect more than one channel, but do not send data.
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In this case the mailbox has only one channel from the point of view of the core that sends the message, right? Actually, the concept of "channel" isn't used in the driver at all.
But yes, it still may be useful to add it to the debug message to know how the caller called the function.
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I meant for consumers it'll probably be better if the mailbox provided more channels, rather than data transfer.
What are you using it for? I use IPM in my branch for IPC subsystem, and so I need more than one channel, but signaling only, no data (data resides in shared memory and access is controlled by two mailbox channels)
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I think we're talking about different things here...
What I did here is a direct mapping of the hardware functionality, with no further abstractions. This handles the SIO mailboxes. According to the docs, there are only two FIFOs (let's call them A and B), one core can only read from A and write to B, while the other can only read from B and write to A. From the point of view of each of the cores, there's only one single channel. Unless we mean different things when we say "channel" in this context.
When you say the data resides in shared memory and the access is controlled by the mailbox channels, I understand that's handled by the IPC mechanism you implemented on top of the mailboxes (ie. a region of memory shared between the cores and a signalling mechanism using the mailboxes). When I mention "data" in the driver, I mean the data that goes through the mailboxes. In the RP2350 each mailbox can hold 4 4-byte messages, for instance. You can ignore the data and use a mailbox for signalling events only, or you can use it to signal an event and carry some data with it (a memory address, for instance).
In the end, the use case will be inter-processor communication, but what I'm doing here is to provide low-level access to the hardware peripheral so that the IPM can be implemented on top of it. For example, using zephyr,mbox-imp as an adaptor.
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Okay, let's leave this to maintainers, because that's really use-case dependent
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@dsseng @dancollins as an additional test, I applied this on top of #93379 and made some changes to do the core-to-core handshake using this driver with the zephyr-ipm,mbox driver as an adaptor. I tested it successfully on a Raspberry Pi Pico 2W. The build steps are the same that Dmitrii shared here with an additional config |
Why enable IPM if your driver is mailbox? Try Could you please make |
Thanks for reviewing. The commit I pointed to was just a quick test for the driver, to show how it works with a simple use case.
Because the test code (soc.c) uses the zephyr IPM driver with this mbox driver as a backend.
As I said before, we're most likely referring to different things when we say IPM/MBOX. I think. The SIO mailboxes is the only way to run core 1 afaict. At least according to the SoC datasheet (section 5.3). I agree that any higher-level IPM mechanisms written on top of that aren't necessary to boot CPU1. This driver does nothing of that, it's simply an implementation of the zephyr mbox interface to the hardware registers of the RP2040/2350
That's true, but is there a strict reason for that? If core 0 is ready to handle interrupts when it does the core 1 boot handshake, why would it be a problem to have the hardware work as intended? Unless there's a risk or a reliability issue in using interrupts at this stage, which I don't know.
That could be a blocker. I don't know if the code in soc.c is supposed to be self-contained. The driver doesn't use any OS service besides enabling/disabling interrupts, though.
I'll check that out, I'm not familiar with that sample. Thanks for the tip. |
This adds a driver for the interprocessor mailbox in the Raspberry Pi Pico SoCs (RP2040/RP2350). The SIO subsystem contains a set of low-latency peripherals, including a pair of mailboxes (FIFOs) for inter-processor communication. One of the FIFOs can only be written by core 0 and read by core 1, the other can only be written by core 1 and read by core 0. According to the datasheets [1] [2], the register interface is the same in both SoCs and the only functional differences are that the mailbox in the RP2040 is 8 entries deep vs 4 in the RP2350, and that the RP2350 defines the same core-specific interrupt number, while the RP2040 defines two different IRQ numbers. Tested on a Raspberry Pi Pico 2W (RP2350). [1]: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf [2]: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf Signed-off-by: Ricardo Cañuelo Navarro <[email protected]>
Add a mailbox (Interprocessor FIFO) node to the RP2040 and RP2350 device trees and a SIO block to hold this and any other future SIO peripherals. This also includes an additional `zephyr,mbox-ipm` node that handles the mailbox for core to core messaging. The device is enabled for the Raspberry Pico Pi 2. Signed-off-by: Ricardo Cañuelo Navarro <[email protected]>
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I don't know for sure, but usually the SoC code tries to use nothing but HAL + maybe CMSIS.
No idea, Dan and I replicated the known good examples (which was the easiest and also makes soc.c self-contained making it upstreamable as a separate bit). https://github.com/raspberrypi/pico-bootrom-rp2350 could give you some insight into what happens at the reset vector for each core. |
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Add support for the inter-processor mailbox peripheral for the RP2040 and RP2350 SoCs. This is a requirement for enabling multi processing (asymmetric) for the Raspberry Pi Pico boards.
Tested on a Raspberry Pi Pico 2W (RP2350).