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Support xspi on rt700 #94921

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265db8a
drivers: xspi: add NXP xspi driver
SuperHeroAbner Sep 1, 2025
ec32e65
dts: Enable the xspi flash and psram cases on NXP RT700
SuperHeroAbner Aug 24, 2025
7acf10d
boards: Update related configuration for RT700 xspi case
SuperHeroAbner Aug 24, 2025
886338e
soc: Update code to get flash size from dts
SuperHeroAbner Sep 1, 2025
e8df10f
samples: Update XSPI memc and flash samples on RT700
SuperHeroAbner Sep 1, 2025
53ea406
west: update hal_nxp
SuperHeroAbner Sep 2, 2025
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28 changes: 28 additions & 0 deletions boards/nxp/mimxrt700_evk/board.c
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Original file line number Diff line number Diff line change
Expand Up @@ -544,6 +544,34 @@ void board_early_init_hook(void)
CLOCK_EnableClock(kCLOCK_Acmp0);
RESET_ClearPeripheralReset(kACMP0_RST_SHIFT_RSTn);
#endif

#if DT_NODE_HAS_STATUS(DT_NODELABEL(xspi0), okay)
POWER_DisablePD(kPDRUNCFG_APD_XSPI0);
POWER_DisablePD(kPDRUNCFG_PPD_XSPI0);
POWER_ApplyPD();
#endif

#if DT_NODE_HAS_STATUS(DT_NODELABEL(xspi1), okay)
xspi_setup_clock(XSPI1, 1U, 1U); /* Audio PLL PDF1 DIV1. */

POWER_DisablePD(kPDRUNCFG_APD_XSPI1);
POWER_DisablePD(kPDRUNCFG_PPD_XSPI1);
POWER_ApplyPD();
#endif

#if DT_NODE_HAS_STATUS(DT_NODELABEL(xspi2), okay)
#if CONFIG_SOC_MIMXRT798S_CM33_CPU0
CLOCK_AttachClk(kMAIN_PLL_PFD3_to_XSPI2);
#elif CONFIG_SOC_MIMXRT798S_CM33_CPU1
CLOCK_AttachClk(kFRO1_DIV1_to_COMMON_BASE);
CLOCK_AttachClk(kCOMMON_BASE_to_XSPI2);
#endif
CLOCK_SetClkDiv(kCLOCK_DivXspi2Clk, 1U);

POWER_DisablePD(kPDRUNCFG_APD_XSPI2);
POWER_DisablePD(kPDRUNCFG_PPD_XSPI2);
POWER_ApplyPD();
#endif
}

static void GlikeyWriteEnable(GLIKEY_Type *base, uint8_t idx)
Expand Down
79 changes: 79 additions & 0 deletions boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -193,4 +193,83 @@
slew-rate = "normal";
};
};

pinmux_xspi0: pinmux_xspi0 {
group0 {
pinmux = <XSPI0_SCK_A_N_PIO6_0>,
<XSPI0_SCK_A_PIO6_1>,
<XSPI0_PCS_A_0_PIO6_2>,
<XSPI0_DATA0_PIO6_3>,
<XSPI0_DATA1_PIO6_4>,
<XSPI0_DATA2_PIO6_5>,
<XSPI0_DATA3_PIO6_6>,
<XSPI0_DQS_A_0_PIO6_7>,
<XSPI0_DATA4_PIO6_8>,
<XSPI0_DATA5_PIO6_9>,
<XSPI0_DATA6_PIO6_10>,
<XSPI0_DATA7_PIO6_11>,
<XSPI0_PCS_A_1_PIO6_12>;
drive-strength = "normal";
slew-rate = "normal";
input-enable;
};
};

pinmux_xspi1: pinmux_xspi1 {
group0 {
pinmux = <XSPI1_PCS_A_0_PIO5_0>,
<XSPI1_DATA0_PIO5_1>,
<XSPI1_DATA1_PIO5_2>,
<XSPI1_DATA2_PIO5_3>,
<XSPI1_DATA3_PIO5_4>,
<XSPI1_DATA4_PIO5_6>,
<XSPI1_DATA5_PIO5_7>,
<XSPI1_DATA6_PIO5_8>,
<XSPI1_DATA7_PIO5_9>,
<XSPI1_DQS_A_0_PIO5_5>,
<XSPI1_SCK_A_PIO5_10>,
<XSPI1_SCK_A_N_PIO5_11>,
<XSPI1_DATA8_PIO5_12>,
<XSPI1_DATA9_PIO5_13>,
<XSPI1_DATA10_PIO5_14>,
<XSPI1_DATA11_PIO5_15>,
<XSPI1_DQS_A_1_PIO5_16>,
<XSPI1_DATA12_PIO5_17>,
<XSPI1_DATA13_PIO5_18>,
<XSPI1_DATA14_PIO5_19>,
<XSPI1_DATA15_PIO5_20>;
drive-strength = "normal";
slew-rate = "normal";
input-enable;
};
};

pinmux_xspi2: pinmux_xspi2 {
group0 {
pinmux = <XSPI2_PCS_A_0_PIO4_0>,
<XSPI2_DATA0_PIO4_1>,
<XSPI2_DATA1_PIO4_2>,
<XSPI2_DATA2_PIO4_3>,
<XSPI2_DATA3_PIO4_4>,
<XSPI2_DQS_A_0_PIO4_5>,
<XSPI2_DATA4_PIO4_6>,
<XSPI2_DATA5_PIO4_7>,
<XSPI2_DATA6_PIO4_8>,
<XSPI2_DATA7_PIO4_9>,
<XSPI2_SCK_A_PIO4_10>,
<XSPI2_SCK_A_N_PIO4_11>,
<XSPI2_DATA8_PIO4_12>,
<XSPI2_DATA9_PIO4_13>,
<XSPI2_DATA10_PIO4_14>,
<XSPI2_DATA11_PIO4_15>,
<XSPI2_DQS_A_1_PIO4_16>,
<XSPI2_DATA12_PIO4_17>,
<XSPI2_DATA13_PIO4_18>,
<XSPI2_DATA14_PIO4_19>,
<XSPI2_DATA15_PIO4_20>;
drive-strength = "normal";
slew-rate = "normal";
input-enable;
};
};
};
139 changes: 103 additions & 36 deletions boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -26,11 +26,12 @@
i2s-tx = &sai0;
sdhc0 = &usdhc0;
rtc = &rtc0;
sram-ext = &psram0;
};

chosen {
zephyr,flash-controller = &mx25um51345g;
zephyr,flash = &mx25um51345g;
zephyr,flash-controller = &flash_controller0;
zephyr,flash = &ext_flash;
zephyr,sram = &sram0;
zephyr,console = &flexcomm0_lpuart0;
zephyr,shell-uart = &flexcomm0_lpuart0;
Expand Down Expand Up @@ -95,6 +96,19 @@
enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
};

memc: memc@8000000 {
status = "okay";
reg = <0x08000000 DT_SIZE_M(32)>;
#address-cells = <1>;
#size-cells = <1>;

psram: memory@8000000 {
compatible = "zephyr,memory-region";
reg = <0x08000000 DT_SIZE_M(32)>;
zephyr,memory-region = "PSRAM";
};
};
};

&ctimer0 {
Expand Down Expand Up @@ -325,47 +339,100 @@ zephyr_lcdif: &lcdif {};

&xspi0 {
status = "okay";
pinctrl-0 = <&pinmux_xspi0>;
pinctrl-names = "default";
byte-order = <3>;
ahb-buffer-write-flush;
ahb-prefetch;

mx25um51345g: mx25um51345g@0 {
compatible = "nxp,xspi-mx25um51345g";
/* MX25UM51245G is 64MB, 512MBit flash part */
size = <DT_SIZE_M(64 * 8)>;
reg = <0>;
spi-max-frequency = <DT_FREQ_M(200)>;
flash_controller0: flash-controller@0 {
status = "okay";
jedec-id = [c2 81 3a];
erase-block-size = <DT_SIZE_K(4)>;
write-block-size = <2>;

partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

/*
* Partition sizes must be aligned
* to the flash memory sector size of 4KB.
*/
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(128)>;
};
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 DT_SIZE_M(7)>;
};
slot1_partition: partition@720000 {
label = "image-1";
reg = <0x00720000 DT_SIZE_M(7)>;
};
storage_partition: partition@E20000 {
label = "storage";
reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>;
compatible = "nxp,xspi-nor";
device-name = "mx25um51345g";
/* MX25UM51245G is 64MB, 512Mbit flash part. */
size = <DT_SIZE_M(64)>;
reg = <0>;
sample-clk-source = <3>;
#address-cells = <1>;
#size-cells = <1>;

ext_flash: flash@38000000 {
compatible = "soc-nv-flash";
reg = <0x38000000 DT_SIZE_M(64)>;
erase-block-size = <DT_SIZE_K(4)>;
write-block-size = <2>;

partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

/*
* Partition sizes must be aligned
* to the flash memory sector size of 4KB.
*/
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(128)>;
};
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 DT_SIZE_M(7)>;
};
slot1_partition: partition@720000 {
label = "image-1";
reg = <0x00720000 DT_SIZE_M(7)>;
};
storage_partition: partition@E20000 {
label = "storage";
reg = <0x00E20000 (DT_SIZE_M(2) - DT_SIZE_K(128))>;
};
};
};
};
};

&xspi1 {
status = "okay";
pinctrl-0 = <&pinmux_xspi1>;
pinctrl-names = "default";
byte-order = <3>;
ahb-buffer-write-flush;
ahb-prefetch;
enable-ahb-write;
/* Connect JP45 1-2 to use XSPI1. */

psram0: memory-controller@0 {
status = "okay";
compatible = "nxp,xspi-psram";
device-name = "w958d6nbkx5l";
size = <DT_SIZE_M(32)>;
reg = <0>;
enable-differential-clk;
sample-clk-source = <3>;
};
};

&xspi2 {
status = "okay";
pinctrl-0 = <&pinmux_xspi2>;
pinctrl-names = "default";
byte-order = <3>;
ahb-buffer-write-flush;
ahb-prefetch;
enable-ahb-write;

psram1: memory-controller@0 {
status = "okay";
compatible = "nxp,xspi-psram";
device-name = "w958d6nbkx4l";
size = <DT_SIZE_M(32)>;
reg = <0>;
enable-differential-clk;
sample-clk-source = <3>;
};
};

zephyr_udc0: &usb0 {
status = "okay";
phy-handle = <&usbphy>;
Expand Down
2 changes: 2 additions & 0 deletions boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -24,4 +24,6 @@ supported:
- usb_device
- watchdog
- hwinfo
- flash
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@SuperHeroAbner as your PR support memc as well, so you need add
- memc
also please update board document

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@SuperHeroAbner SuperHeroAbner Aug 28, 2025 •
edited
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How to trigger your online test? My local test is normal and it actually takes about 10s to finish all test with final log 'Read data matches written data'. In middle state it has log like 'Check (3465/4095) passed!'. I'm not sure is the timeout check is only targeting to the final log and timeout after 10s.

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@hakehuang hakehuang Aug 28, 2025 •
edited
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How to trigger your online test? My local test is normal and it actually takes about 10s to finish all test with final log 'Read data matches written data'. In middle state it has log like 'Check (3465/4095) passed!'. I'm not sure is the timeout check is only targeting to the final log and timeout after 10s.

I test your PR locally, still the same. is there any reused pins with spi_loopback? from debug info, looks like the mem clock is not stable for my boards, but this could be a general problem

image

and I add a print in the first loop, which can run to the end but with r/w error.

index 6f58db196ff..817c6c3f528 100644
--- a/samples/drivers/memc/src/main.c
+++ b/samples/drivers/memc/src/main.c
@@ -86,11 +86,16 @@ int main(void)
        /* Copy write buffer into memc region */
        for (i = 0, j = 0; j < (MEMC_SIZE / BUF_SIZE); i += BUF_SIZE, j++) {
                memcpy(memc + i, memc_write_buffer, BUF_SIZE);
+               printk("Writing %d\n", i);
        }
+
+       printk("Writing to memory region done %d %d\n\n", i, j);
        /* Copy any remaining space bytewise */
        for (; i < MEMC_SIZE; i++) {
                memc[i] = memc_write_buffer[i];
+               printk("Writing %d\n", i);
        }
+       printk("Writing to remain memory region done\n\n");
        /* Read from memc region into buffer */
        for (i = 0, j = 0; j < (MEMC_SIZE / BUF_SIZE); i += BUF_SIZE, j++) {
                memcpy(memc_read_buffer, memc + i, BUF_SIZE);

log below

Writing 4192256
Writing 4193280
Writing to memory region done 4194304 4096

Writing to remain memory region done

Error: read data differs in range [0x0- 0x3ff]

and I meet such issue on two boards, so please check the memc timing @SuperHeroAbner

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@hakehuang Please check the JP45, should connect 1-2. Shall I add this in certain place in doc?

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@hakehuang hakehuang Aug 29, 2025 •
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@SuperHeroAbner thanks, with JP45 move to 1-2 the memc case pass. please update - memc in board support yaml file
also please update board document

- memc
vendor: nxp
21 changes: 21 additions & 0 deletions boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@
sw0 = &user_button_1;
ambient-temp0 = &p3t1755;
rtc = &rtc1;
sram-ext = &psram;
};

chosen {
Expand Down Expand Up @@ -114,3 +115,23 @@
&mbox1_b {
status = "okay";
};

&xspi2 {
status = "okay";
pinctrl-0 = <&pinmux_xspi2>;
pinctrl-names = "default";
byte-order = <3>;
ahb-buffer-write-flush;
ahb-prefetch;
enable-ahb-write;

psram: memory-controller@0 {
status = "okay";
compatible = "nxp,xspi-psram";
device-name = "w958d6nbkx4l";
size = <DT_SIZE_M(32)>;
reg = <0>;
enable-differential-clk;
sample-clk-source = <3>;
};
};
2 changes: 2 additions & 0 deletions boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -19,4 +19,6 @@ supported:
- uart
- adc
- i3c
- flash
- memc
vendor: nxp
11 changes: 11 additions & 0 deletions drivers/flash/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,7 @@ zephyr_library_sources_ifdef(CONFIG_FLASH_INFINEON_CAT1 flash_ifx_cat1.c)
zephyr_library_sources_ifdef(CONFIG_FLASH_MCUX_FLEXSPI_HYPERFLASH flash_mcux_flexspi_hyperflash.c)
zephyr_library_sources_ifdef(CONFIG_FLASH_MCUX_FLEXSPI_MX25UM51345G flash_mcux_flexspi_mx25um51345g.c)
zephyr_library_sources_ifdef(CONFIG_FLASH_MCUX_FLEXSPI_NOR flash_mcux_flexspi_nor.c)
zephyr_library_sources_ifdef(CONFIG_FLASH_MCUX_XSPI flash_mcux_xspi.c)
zephyr_library_sources_ifdef(CONFIG_FLASH_MSPI_ATXP032 flash_mspi_atxp032.c)
zephyr_library_sources_ifdef(CONFIG_FLASH_MSPI_EMUL_DEVICE flash_mspi_emul_device.c)
zephyr_library_sources_ifdef(CONFIG_FLASH_MSPI_IS25XX0XX flash_mspi_is25xX0xx.c)
Expand Down Expand Up @@ -100,6 +101,11 @@ if(CONFIG_FLASH_MCUX_FLEXSPI_XIP)
endif()
endif()

if(CONFIG_FLASH_MCUX_XSPI_XIP)
zephyr_code_relocate(FILES flash_mcux_xspi.c LOCATION ${CONFIG_FLASH_MCUX_XSPI_XIP_MEM}_TEXT)
zephyr_code_relocate(FILES flash_mcux_xspi.c LOCATION ${CONFIG_FLASH_MCUX_XSPI_XIP_MEM}_RODATA)
endif()

if(CONFIG_SOC_FLASH_STM32)
zephyr_library_sources_ifdef(CONFIG_FLASH_EX_OP_ENABLED flash_stm32_ex_op.c)
if(CONFIG_SOC_SERIES_STM32H7X)
Expand Down Expand Up @@ -160,6 +166,11 @@ zephyr_library_include_directories_ifdef(
${ZEPHYR_BASE}/drivers/memc
)

zephyr_library_include_directories_ifdef(
CONFIG_FLASH_MCUX_XSPI
${ZEPHYR_BASE}/drivers/memc
)

zephyr_library_sources_ifdef(CONFIG_FLASH_NXP_S32_QSPI_NOR flash_nxp_s32_qspi_nor.c)
zephyr_library_sources_ifdef(CONFIG_FLASH_NXP_S32_QSPI_HYPERFLASH flash_nxp_s32_qspi_hyperflash.c)
if(CONFIG_FLASH_NXP_S32_QSPI_NOR OR CONFIG_FLASH_NXP_S32_QSPI_HYPERFLASH)
Expand Down
12 changes: 12 additions & 0 deletions drivers/flash/Kconfig.mcux
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Original file line number Diff line number Diff line change
Expand Up @@ -118,3 +118,15 @@ choice FLASH_LOG_LEVEL_CHOICE
endchoice

endif # DT_HAS_NXP_IMX_FLEXSPI_ENABLED

config FLASH_MCUX_XSPI
bool "MCUX XSPI flash driver"
default y
depends on DT_HAS_NXP_XSPI_NOR_ENABLED
select MEMC
select MEMC_MCUX_XSPI
select FLASH_HAS_DRIVER_ENABLED
select FLASH_HAS_PAGE_LAYOUT
select FLASH_HAS_EXPLICIT_ERASE
help
Enable the mcux xspi flash driver.
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