Add support Clock Control driver for Renesas RZ/T2M, N2L

drivers/clock_control/CMakeLists.txt

@@ -45,6 +45,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA_CGC      clock_cont
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_ROOT     clock_control_renesas_rx_root_cgc.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_PLL      clock_control_renesas_rx_pll_cgc.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RX_PCLK     clock_control_renesas_rx_pclk_cgc.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RZ_CGC      clock_control_renesas_rz_cgc.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RZ_CPG      clock_control_renesas_rz_cpg.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AMBIQ               clock_control_ambiq.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_PWM                 clock_control_pwm.c)

drivers/clock_control/Kconfig

@@ -96,6 +96,8 @@ source "drivers/clock_control/Kconfig.renesas_rx_cgc"
 
 source "drivers/clock_control/Kconfig.renesas_rz_cpg"
 
+source "drivers/clock_control/Kconfig.renesas_rz_cgc"
+
 source "drivers/clock_control/Kconfig.max32"
 
 source "drivers/clock_control/Kconfig.ambiq"

drivers/clock_control/Kconfig.renesas_rz_cgc

@@ -0,0 +1,12 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config CLOCK_CONTROL_RENESAS_RZ_CGC
+	bool "Renesas RZ Clock Control Driver"
+	default y
+	depends on DT_HAS_RENESAS_RZ_CGC_ENABLED
+	select USE_RZ_FSP_CGC
+	help
+	  Enable support for Renesas RZ CGC Clock Generator Circuit (CGC) driver.
+	  The CGC driver supports only module's clocks.
+	  The PLLs and core clocks are not configured by the CGC driver.

drivers/clock_control/clock_control_renesas_rz_cgc.c

@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/dt-bindings/clock/renesas_rztn_clock.h>
+#include <zephyr/kernel.h>
+#include "bsp_api.h"
+
+#define DT_DRV_COMPAT renesas_rz_cgc
+
+static int clock_control_renesas_rz_on(const struct device *dev, clock_control_subsys_t sys)
+{
+	if (!dev || !sys) {
+		return -EINVAL;
+	}
+
+	uint32_t *clock_id = (uint32_t *)sys;
+
+	uint32_t ip = (*clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT;
+	uint32_t ch = (*clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT;
+
+	R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+	switch (ip) {
+	case RZ_IP_BSC:
+		R_BSP_MODULE_START(FSP_IP_BSC, ch);
+		break;
+	case RZ_IP_XSPI:
+		R_BSP_MODULE_START(FSP_IP_XSPI, ch);
+		break;
+	case RZ_IP_SCI:
+		R_BSP_MODULE_START(FSP_IP_SCI, ch);
+		break;
+	case RZ_IP_IIC:
+		R_BSP_MODULE_START(FSP_IP_IIC, ch);
+		break;
+	case RZ_IP_SPI:
+		R_BSP_MODULE_START(FSP_IP_SPI, ch);
+		break;
+	case RZ_IP_GPT:
+		R_BSP_MODULE_START(FSP_IP_GPT, ch);
+		break;
+	case RZ_IP_ADC12:
+		R_BSP_MODULE_START(FSP_IP_ADC12, ch);
+		break;
+	case RZ_IP_CMT:
+		R_BSP_MODULE_START(FSP_IP_CMT, ch);
+		break;
+	case RZ_IP_CMTW:
+		R_BSP_MODULE_START(FSP_IP_CMTW, ch);
+		break;
+	case RZ_IP_CANFD:
+		R_BSP_MODULE_START(FSP_IP_CANFD, ch);
+		break;
+	case RZ_IP_GMAC:
+		R_BSP_MODULE_START(FSP_IP_GMAC, ch);
+		break;
+	case RZ_IP_ETHSW:
+		R_BSP_MODULE_START(FSP_IP_ETHSW, ch);
+		break;
+	case RZ_IP_USBHS:
+		R_BSP_MODULE_START(FSP_IP_USBHS, ch);
+		break;
+	case RZ_IP_RTC:
+		R_BSP_MODULE_START(FSP_IP_RTC, ch);
+		break;
+	default:
+		R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+		return -EINVAL; /* Invalid FSP IP Module */
+	}
+	R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+	return 0;
+}
+
+static int clock_control_renesas_rz_off(const struct device *dev, clock_control_subsys_t sys)
+{
+	if (!dev || !sys) {
+		return -EINVAL;
+	}
+
+	uint32_t *clock_id = (uint32_t *)sys;
+
+	uint32_t ip = (*clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT;
+	uint32_t ch = (*clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT;
+
+	R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_RESET);
+	switch (ip) {
+	case RZ_IP_BSC:
+		R_BSP_MODULE_STOP(FSP_IP_BSC, ch);
+		break;
+	case RZ_IP_XSPI:
+		R_BSP_MODULE_STOP(FSP_IP_XSPI, ch);
+		break;
+	case RZ_IP_SCI:
+		R_BSP_MODULE_STOP(FSP_IP_SCI, ch);
+		break;
+	case RZ_IP_IIC:
+		R_BSP_MODULE_STOP(FSP_IP_IIC, ch);
+		break;
+	case RZ_IP_SPI:
+		R_BSP_MODULE_STOP(FSP_IP_SPI, ch);
+		break;
+	case RZ_IP_GPT:
+		R_BSP_MODULE_STOP(FSP_IP_GPT, ch);
+		break;
+	case RZ_IP_ADC12:
+		R_BSP_MODULE_STOP(FSP_IP_ADC12, ch);
+		break;
+	case RZ_IP_CMT:
+		R_BSP_MODULE_STOP(FSP_IP_CMT, ch);
+		break;
+	case RZ_IP_CMTW:
+		R_BSP_MODULE_STOP(FSP_IP_CMTW, ch);
+		break;
+	case RZ_IP_CANFD:
+		R_BSP_MODULE_STOP(FSP_IP_CANFD, ch);
+		break;
+	case RZ_IP_GMAC:
+		R_BSP_MODULE_STOP(FSP_IP_GMAC, ch);
+		break;
+	case RZ_IP_ETHSW:
+		R_BSP_MODULE_STOP(FSP_IP_ETHSW, ch);
+		break;
+	case RZ_IP_USBHS:
+		R_BSP_MODULE_STOP(FSP_IP_USBHS, ch);
+		break;
+	case RZ_IP_RTC:
+		R_BSP_MODULE_STOP(FSP_IP_RTC, ch);
+		break;
+	default:
+		R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+		return -EINVAL; /* Invalid FSP IP Module */
+	}
+	R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_RESET);
+
+	return 0;
+}
+
+static int clock_control_renesas_rz_get_rate(const struct device *dev, clock_control_subsys_t sys,
+					     uint32_t *rate)
+{
+	if (!dev || !sys || !rate) {
+		return -EINVAL;
+	}
+
+	uint32_t *clock_id = (uint32_t *)sys;
+	fsp_priv_clock_t clk_src = (*clock_id & RZ_CLOCK_MASK) >> RZ_CLOCK_SHIFT;
+	uint32_t clk_hz = R_FSP_SystemClockHzGet(clk_src);
+
+	*rate = clk_hz;
+
+	return 0;
+}
+
+static DEVICE_API(clock_control, rz_clock_control_driver_api) = {
+	.on = clock_control_renesas_rz_on,
+	.off = clock_control_renesas_rz_off,
+	.get_rate = clock_control_renesas_rz_get_rate,
+};
+
+static int clock_control_rz_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return 0;
+}
+
+DEVICE_DT_INST_DEFINE(0, clock_control_rz_init, NULL, NULL, NULL, PRE_KERNEL_1,
+		      CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &rz_clock_control_driver_api);

dts/arm/renesas/rz/rzn/r9a07g084.dtsi

@@ -5,8 +5,10 @@
 
 #include <mem.h>
 #include <arm/armv8-r.dtsi>
+#include <freq.h>
 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
 #include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/clock/renesas_rztn_clock.h>
 #include <zephyr/dt-bindings/i2c/i2c.h>
 
 / {
@@ -34,6 +36,12 @@
 		interrupt-parent = <&gic>;
 	};
 
+	osc: osc {
+		compatible = "fixed-clock";
+		clock-frequency = <DT_FREQ_M(25)>;
+		#clock-cells = <0>;
+	};
+
 	soc {
 		interrupt-parent = <&gic>;
 
@@ -90,6 +98,111 @@
 			};
 		};
 
+		cgc: clock-controller@80280000 {
+			compatible = "renesas,rz-cgc";
+			reg = <0x80280000 0x314>, <0x81280000 0x324>;
+			clocks = <&osc>;
+			#clock-cells = <1>;
+			status = "okay";
+
+			loco: loco {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_K(240)>;
+				#clock-cells = <0>;
+				status = "okay";
+			};
+
+			pll1: pll1 {
+				compatible = "renesas,rz-cgc-pll";
+				state = "initial";
+			};
+
+			iclk: iclk {
+				compatible = "renesas,rz-cgc-sys-clock";
+				clock-frequency = <DT_FREQ_M(200)>;
+
+				cpu0clk: cpu0clk {
+					compatible = "renesas,rz-cgc-sys-clock";
+					mul = <1>;
+				};
+
+				ckio: ckio {
+					compatible = "renesas,rz-cgc-sys-clock";
+					div = <4>;
+				};
+			};
+
+			eth_refclk: eth_refclk {
+				compatible = "renesas,rz-cgc-subclk";
+				eth-phy-source = "main";
+			};
+
+			canfdclk: canfdclk {
+				compatible = "renesas,rz-cgc-subclk";
+				canfd-source = <1>;
+			};
+
+			xspi_clk0: xspi_clk0 {
+				compatible = "renesas,rz-cgc-subclk";
+				xspi-clk-frequency = <12500000>;
+			};
+
+			xspi_clk1: xspi_clk1 {
+				compatible = "renesas,rz-cgc-subclk";
+				xspi-clk-frequency = <12500000>;
+			};
+
+			sci0asyncclk: sci0asyncclk {
+				compatible = "renesas,rz-cgc-subclk";
+				clock-frequency = <DT_FREQ_M(96)>;
+			};
+
+			sci1asyncclk: sci1asyncclk {
+				compatible = "renesas,rz-cgc-subclk";
+				clock-frequency = <DT_FREQ_M(96)>;
+			};
+
+			sci2asyncclk: sci2asyncclk {
+				compatible = "renesas,rz-cgc-subclk";
+				clock-frequency = <DT_FREQ_M(96)>;
+			};
+
+			sci3asyncclk: sci3asyncclk {
+				compatible = "renesas,rz-cgc-subclk";
+				clock-frequency = <DT_FREQ_M(96)>;
+			};
+
+			sci4asyncclk: sci4asyncclk {
+				compatible = "renesas,rz-cgc-subclk";
+				clock-frequency = <DT_FREQ_M(96)>;
+			};
+
+			sci5asyncclk: sci5asyncclk {
+				compatible = "renesas,rz-cgc-subclk";
+				clock-frequency = <DT_FREQ_M(96)>;
+			};
+
+			spi0asyncclk: spi0asyncclk {
+				compatible = "renesas,rz-cgc-subclk";
+				clock-frequency = <DT_FREQ_M(96)>;
+			};
+
+			spi1asyncclk: spi1asyncclk {
+				compatible = "renesas,rz-cgc-subclk";
+				clock-frequency = <DT_FREQ_M(96)>;
+			};
+
+			spi2asyncclk: spi2asyncclk {
+				compatible = "renesas,rz-cgc-subclk";
+				clock-frequency = <DT_FREQ_M(96)>;
+			};
+
+			spi3asyncclk: spi3asyncclk {
+				compatible = "renesas,rz-cgc-subclk";
+				clock-frequency = <DT_FREQ_M(96)>;
+			};
+		};
+
 		adc0: adc0@90004000 {
 			compatible = "renesas,rz-adc";
 			reg = <0x90004000 0x1000>;