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drivers: i2s: add sai support for stm32wba55 #94960

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drivers: i2s: add sai support for stm32wba55 #94960

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b4a1005
dt-bindings: clock: stm32wba add SAI1_SEL()
mariopaja Aug 25, 2025
2107757
dts: bindings: clock: stm32wba pll clock add div-p
mariopaja Aug 25, 2025
a6cfd97
dts: st: wba: add sai1 node
mariopaja Aug 21, 2025
2a5034f
samples: i2s: output: add nucleo_wba55cg
mariopaja Aug 25, 2025
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25 changes: 25 additions & 0 deletions dts/arm/st/wba/stm32wba55.dtsi
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2023 STMicroelectronics
* Copyright (c) 2025 Mario Paja
*
* SPDX-License-Identifier: Apache-2.0
*/
Expand All @@ -8,6 +9,30 @@
/ {
soc {
compatible = "st,stm32wba55", "st,stm32wba", "simple-bus";

sai1_a: sai1@40015404 {
compatible = "st,stm32-sai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015404 0x20>;
clocks = <&rcc STM32_CLOCK(APB2, 21)>,
<&rcc STM32_SRC_PLL1_P SAI1_SEL(0)>;
dmas = <&gpdma1 1 17 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH |
STM32_DMA_16BITS)>;
status = "disabled";
};

sai1_b: sai1@40015424 {
compatible = "st,stm32-sai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015424 0x20>;
clocks = <&rcc STM32_CLOCK(APB2, 21)>,
<&rcc STM32_SRC_PLL1_P SAI1_SEL(0)>;
dmas = <&gpdma1 0 18 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH |
STM32_DMA_16BITS)>;
status = "disabled";
};
};
};

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7 changes: 7 additions & 0 deletions dts/bindings/clock/st,stm32wba-pll-clock.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -51,6 +51,13 @@ properties:
PLLx multiplication factor for VCO
Valid range: 4 - 512
div-p:
type: int
required: true
description: |
PLLx DIVP division factor
Valid range: 1 - 128
div-q:
type: int
description: |
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1 change: 1 addition & 0 deletions include/zephyr/dt-bindings/clock/stm32wba_clock.h
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Expand Up @@ -69,6 +69,7 @@
#define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR1_REG)
#define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 31, CCIPR1_REG)
/** CCIPR2 devices */
#define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 5, CCIPR2_REG)
#define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
/** CCIPR3 devices */
#define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG)
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1 change: 1 addition & 0 deletions samples/drivers/i2s/output/boards/nucleo_wba55cg.conf
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@@ -0,0 +1 @@
CONFIG_HEAP_MEM_POOL_SIZE=4192
45 changes: 45 additions & 0 deletions samples/drivers/i2s/output/boards/nucleo_wba55cg.overlay
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@@ -0,0 +1,45 @@
/*
* Copyright (c) 2025 Mario Paja
*
* SPDX-License-Identifier: Apache-2.0
*/

/ {
aliases {
i2s-tx = &sai1_b;
};
};

&pll1 {
/* 43.526KHz (-1.3% Error) */
div-m = <4>;
mul-n = <19>;
div-r = <2>;
div-q = <2>;
div-p = <14>;
clocks = <&clk_hse>;
status = "okay";
};

&gpdma1 {
status = "okay";
};

/* SAI MCLK conflicts with SPI SCK */
/* SAI FS conflicts with LPUART TX */
&sai1_b {
pinctrl-0 = <&sai1_mclk_b_pb4 &sai1_sd_b_pb7 &sai1_fs_b_pb5 &sai1_sck_b_pb6>;
pinctrl-names = "default";
status = "okay";
mclk-enable;
mclk-divider = "div-256";
dma-names = "tx";
};

&spi1 {
status = "disabled";
};

&lpuart1 {
status = "disabled";
};
1 change: 1 addition & 0 deletions ...drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/clear_clocks.overlay
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Expand Up @@ -21,6 +21,7 @@
&pll1 {
/delete-property/ div-m;
/delete-property/ mul-n;
/delete-property/ div-p;
/delete-property/ div-q;
/delete-property/ div-r;
/delete-property/ clocks;
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1 change: 1 addition & 0 deletions .../drivers/clock_control/stm32_clock_configuration/stm32wba_core/boards/pll_hse_100.overlay
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Expand Up @@ -17,6 +17,7 @@
&pll1 {
div-m = <8>;
mul-n = <100>;
div-p = <2>;
div-q = <2>;
div-r = <4>;
clocks = <&clk_hse>;
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1 change: 1 addition & 0 deletions ...s/clock_control/stm32_clock_configuration/stm32wba_core/boards/pll_hse_100_ahb_50.overlay
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Expand Up @@ -17,6 +17,7 @@
&pll1 {
div-m = <8>;
mul-n = <100>;
div-p = <2>;
div-q = <2>;
div-r = <4>;
clocks = <&clk_hse>;
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