arch: arm: cortex_m: save and restore additional CPU state in S2RAM #95051
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added 3 commits
August 27, 2025 11:04
The current implementation of S2RAM for Cortex-M does not work on SoCs with multiple CPUs. Make sure it is not possible to build S2RAM on such SoCs. Signed-off-by: Mathieu CHOPLAIN <[email protected]>
Use the toolchain-agnostic Z_GENERIC_SECTION() macro in place of the GCC-ism used to place the CPU context in a specific section. Also wrap the section selector into a new "__s2ram_ctx" macro to allow re-use for other structures S2RAM might have to save. Signed-off-by: Mathieu CHOPLAIN <[email protected]>
Save/restore additional CPU state when entering/existing S2RAM states: the SCB, MPU and FPU (if enabled) registers are now saved and restored appropriately at architecture level. Implement the feature in C to reduce the amount of assembly required. Signed-off-by: Mathieu CHOPLAIN <[email protected]>
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CI breakage is expected (Nordic board doesn't reserve enough room for the now-larger state) |
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Final step of #90001: edit the architecture layer to automatically handle save/restore of CPU state that goes beyond the mere general-purpose and special registers.
Also cleans up the implementation a tiny bit, and add an assertion to prevent usage of S2RAM in unsupported configuration.
NOTE: PR is marked as draft for now as NVIC save/restore is not yet implemented. There is also some cleanup to be done.