boards: mps4: Enable non-secure variant support

boards/arm/mps4/Kconfig

@@ -4,3 +4,4 @@
 config BOARD_MPS4
 	select BUILD_WITH_TFM if BOARD_MPS4_CORSTONE315_FVP_NS || BOARD_MPS4_CORSTONE320_FVP_NS
 	select TRUSTED_EXECUTION_NONSECURE if BOARD_MPS4_CORSTONE315_FVP_NS || BOARD_MPS4_CORSTONE320_FVP_NS
+	select USE_DT_CODE_PARTITION if BOARD_MPS4_CORSTONE315_FVP_NS || BOARD_MPS4_CORSTONE320_FVP_NS

boards/arm/mps4/board.cmake

@@ -33,7 +33,16 @@ if(CONFIG_ARM_PAC OR CONFIG_ARM_BTI)
 endif()
 
 if(CONFIG_BUILD_WITH_TFM)
-  set(ARMFVP_FLAGS ${ARMFVP_FLAGS} -a ${APPLICATION_BINARY_DIR}/zephyr/tfm_merged.hex)
+  # Workaround: Use binary (.bin) format images until TF-M supports generating them in hex (.hex)
+  # format. The image load addresses are referred from the TF-M official documentation at:
+  # https://trustedfirmware-m.readthedocs.io/en/latest/platform/arm/mps4/corstone320/README.html
+  set(ARMFVP_FLAGS ${ARMFVP_FLAGS}
+    --data ${APPLICATION_BINARY_DIR}/tfm/bin/bl1_1.bin@0x11000000
+    --data ${APPLICATION_BINARY_DIR}/tfm/bin/cm_provisioning_bundle.bin@0x12024000
+    --data ${APPLICATION_BINARY_DIR}/tfm/bin/dm_provisioning_bundle.bin@0x1202aa00
+    --data ${APPLICATION_BINARY_DIR}/tfm/bin/bl2_signed.bin@0x12031400
+    -a ${APPLICATION_BINARY_DIR}/zephyr/tfm_merged.hex
+  )
 endif()
 
 # FVP Parameters

boards/arm/mps4/mps4_common.dtsi

@@ -97,21 +97,6 @@
 		zephyr,memory-region = "NULL_PTR_DETECT";
 		zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_FLASH)>;
 	};
-
-	/* DDR4 - 2G, alternates non-secure/secure every 256M */
-	ddr4: memory@60000000 {
-		device_type = "memory";
-		compatible = "zephyr,memory-region";
-		reg = <0x60000000 DT_SIZE_M(256)
-		       0x70000000 DT_SIZE_M(256)
-		       0x80000000 DT_SIZE_M(256)
-		       0x90000000 DT_SIZE_M(256)
-		       0xa0000000 DT_SIZE_M(256)
-		       0xb0000000 DT_SIZE_M(256)
-		       0xc0000000 DT_SIZE_M(256)
-		       0xd0000000 DT_SIZE_M(256)>;
-		zephyr,memory-region = "DDR4";
-	};
 };
 
 &nvic {

boards/arm/mps4/mps4_common_ns.dtsi

@@ -0,0 +1,46 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <[email protected]>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/ {
+	reserved_memory: reserved-memory@28000000 {
+		compatible = "soc-nv-flash";
+		reg = <0x28000000 DT_SIZE_M(8)>;
+		erase-block-size = <65536>;
+		write-block-size = <4>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/* The memory regions defined below must match what the TF-M
+			 * project has defined for that board - a single image boot is
+			 * assumed. Please see the memory layout in:
+			 * https://git.trustedfirmware.org/plugins/gitiles/TF-M/trusted-firmware-m.git/+/refs/heads/main/platform/ext/target/arm/mps4/common/partition/flash_layout.h
+			 */
+			slot0_partition: partition@0 {
+				reg = <0x00000000 DT_SIZE_K(512)>;
+			};
+
+			slot0_ns_partition: partition@80000 {
+				reg = <0x00080000 DT_SIZE_M(3)>;
+			};
+
+			slot1_partition: partition@380000 {
+				reg = <0x00380000 DT_SIZE_K(512)>;
+			};
+
+			slot1_ns_partition: partition@400000 {
+				reg = <0x00400000 DT_SIZE_M(3)>;
+			};
+
+			scratch_partition: partition@700000 {
+				reg = <0x00700000 DT_SIZE_K(512)>;
+			};
+		};
+	};
+};

boards/arm/mps4/mps4_corstone315_fvp.dts

@@ -83,6 +83,59 @@
 		zephyr,memory-region = "ISRAM";
 	};
 
+	/* The DDR4 node and zephyr,memory-region follow the naming convention
+	 * ddr4_$IDAUID_$SECURITY_FLAG except for the default region of board
+	 * which is named as "DDR4" to be compatible with existing
+	 * samples/tests that expect DDR4 node and region to be of the same name.
+	 */
+	ddr4_6_ns: memory@60000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x60000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_6_NS";
+	};
+
+	ddr4: memory@70000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x70000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4";
+	};
+
+	ddr4_8_ns: memory@80000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x80000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_8_NS";
+	};
+
+	ddr4_9_s: memory@90000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x90000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_9_S";
+	};
+
+	ddr4_a_ns: memory@a0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xa0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_A_NS";
+	};
+
+	ddr4_b_s: memory@b0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xb0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_B_S";
+	};
+
+	ddr4_c_ns: memory@c0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xc0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_C_NS";
+	};
+
+	ddr4_d_s: memory@d0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xd0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_D_S";
+	};
+
 	soc {
 		peripheral@50000000 {
 			#address-cells = <1>;

boards/arm/mps4/mps4_corstone315_fvp_ns.dts

@@ -11,6 +11,8 @@
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
 
+#include "mps4_common_ns.dtsi"
+
 / {
 	compatible = "arm,mps4-fvp";
 	#address-cells = <1>;
@@ -20,7 +22,8 @@
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
 		zephyr,sram = &ram;
-		zephyr,flash = &code;
+		zephyr,flash = &reserved_memory;
+		zephyr,code-partition = &slot0_ns_partition;
 	};
 
 	cpus {
@@ -68,21 +71,40 @@
 		zephyr,memory-region = "ISRAM";
 	};
 
+	/* The DDR4 node and zephyr,memory-region follow the naming convention
+	 * ddr4_$IDAUID_$SECURITY_FLAG except for the default region of board
+	 * which is named as "DDR4" to be compatible with existing
+	 * samples/tests that expect DDR4 node and region to be of the same name.
+	 */
+	ddr4: memory@60000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x60000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4";
+	};
+
+	ddr4_8_ns: memory@80000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x80000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_8_NS";
+	};
+
+	ddr4_a_ns: memory@a0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xa0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_A_NS";
+	};
+
+	ddr4_c_ns: memory@c0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xc0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_C_NS";
+	};
+
 	reserved-memory {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
 
-		/* The memory regions defined below must match what the TF-M
-		 * project has defined for that board - a single image boot is
-		 * assumed. Please see the memory layout in:
-		 * https://git.trustedfirmware.org/plugins/gitiles/TF-M/trusted-firmware-m.git/+/HEAD/platform/ext/target/arm/mps4/common/partition/flash_layout.h
-		 */
-
-		code: memory@28080000 {
-			reg = <0x28080000 DT_SIZE_K(512)>;
-		};
-
 		ram: memory@21020000 {
 			reg = <0x21020000 DT_SIZE_M(1)>;
 		};

boards/arm/mps4/mps4_corstone315_fvp_ns.yaml

@@ -7,6 +7,9 @@ type: mcu
 arch: arm
 ram: 1024
 flash: 512
+simulation:
+  - name: armfvp
+    exec: FVP_Corstone_SSE-315
 toolchain:
   - gnuarmemb
   - zephyr

boards/arm/mps4/mps4_corstone320_fvp.dts

@@ -83,6 +83,59 @@
 		zephyr,memory-region = "ISRAM";
 	};
 
+	/* The DDR4 node and zephyr,memory-region follow the naming convention
+	 * ddr4_$IDAUID_$SECURITY_FLAG except for the default region of board
+	 * which is named as "DDR4" to be compatible with existing
+	 * samples/tests that expect DDR4 node and region to be of the same name.
+	 */
+	ddr4_6_ns: memory@60000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x60000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_6_NS";
+	};
+
+	ddr4: memory@70000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x70000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4";
+	};
+
+	ddr4_8_ns: memory@80000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x80000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_8_NS";
+	};
+
+	ddr4_9_s: memory@90000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x90000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_9_S";
+	};
+
+	ddr4_a_ns: memory@a0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xa0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_A_NS";
+	};
+
+	ddr4_b_s: memory@b0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xb0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_B_S";
+	};
+
+	ddr4_c_ns: memory@c0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xc0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_C_NS";
+	};
+
+	ddr4_d_s: memory@d0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xd0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_D_S";
+	};
+
 	soc {
 		peripheral@50000000 {
 			#address-cells = <1>;

boards/arm/mps4/mps4_corstone320_fvp_ns.dts

@@ -11,6 +11,8 @@
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
 
+#include "mps4_common_ns.dtsi"
+
 / {
 	compatible = "arm,mps4-fvp";
 	#address-cells = <1>;
@@ -20,7 +22,8 @@
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
 		zephyr,sram = &ram;
-		zephyr,flash = &code;
+		zephyr,flash = &reserved_memory;
+		zephyr,code-partition = &slot0_ns_partition;
 	};
 
 	cpus {
@@ -68,21 +71,40 @@
 		zephyr,memory-region = "ISRAM";
 	};
 
+	/* The DDR4 node and zephyr,memory-region follow the naming convention
+	 * ddr4_$IDAUID_$SECURITY_FLAG except for the default region of board
+	 * which is named as "DDR4" to be compatible with existing
+	 * samples/tests that expect DDR4 node and region to be of the same name.
+	 */
+	ddr4: memory@60000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x60000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4";
+	};
+
+	ddr4_8_ns: memory@80000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x80000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_8_NS";
+	};
+
+	ddr4_a_ns: memory@a0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xa0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_A_NS";
+	};
+
+	ddr4_c_ns: memory@c0000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0xc0000000 DT_SIZE_M(256)>;
+		zephyr,memory-region = "DDR4_C_NS";
+	};
+
 	reserved-memory {
 		#address-cells = <1>;
 		#size-cells = <1>;
 		ranges;
 
-		/* The memory regions defined below must match what the TF-M
-		 * project has defined for that board - a single image boot is
-		 * assumed. Please see the memory layout in:
-		 * https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps4/corstone320/common/partition/flash_layout.h
-		 */
-
-		code: memory@28080000 {
-			reg = <0x28080000 DT_SIZE_K(512)>;
-		};
-
 		ram: memory@21020000 {
 			reg = <0x21020000 DT_SIZE_M(1)>;
 		};

boards/arm/mps4/mps4_corstone320_fvp_ns.yaml

@@ -7,6 +7,9 @@ type: mcu
 arch: arm
 ram: 1024
 flash: 512
+simulation:
+  - name: armfvp
+    exec: FVP_Corstone_SSE-320
 toolchain:
   - gnuarmemb
   - zephyr