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NXP support lptmr tickless function #95143

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NXP support lptmr tickless function #95143

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@yongxu-wang15 yongxu-wang15 commented Aug 29, 2025 •
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  1. added lptmr tickless function
  2. verified in imx95 m7 core which enabled PM and tickless
    Uploading image.png…

@yongxu-wang15 yongxu-wang15 force-pushed the NXP-support-lptmr-tickless-function branch from 2cf7357 to 0b787a8 Compare September 24, 2025 01:58
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Updated to fixed dts conflict with newly commit modification.

Hi, this PR is aim to support nxp lptmr tickless function, and supported it in imx95 m7, can you help review it when you time free?

Thanks

@yongxu-wang15 yongxu-wang15 force-pushed the NXP-support-lptmr-tickless-function branch 2 times, most recently from a4522f5 to 5b1791a Compare September 29, 2025 01:52
@zephyrbot zephyrbot added platform: NXP NXP area: Tests Issues related to a particular existing or missing test area: Boards/SoCs labels Sep 29, 2025
@zephyrbot zephyrbot requested a review from nashif September 29, 2025 01:54
@yongxu-wang15 yongxu-wang15 force-pushed the NXP-support-lptmr-tickless-function branch from 5b1791a to 099ead3 Compare September 29, 2025 05:15
@decsny
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decsny commented Sep 29, 2025

@mmahadevan108 please help review this

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ping @henrikbrixandersen @DerekSnell
There is a mention in the Reference Manual that "If LPTMR is enabled, you must alter CMR only if TCF = 1." Is this accounted for in your PR.

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ping @henrikbrixandersen @DerekSnell There is a mention in the Reference Manual that "If LPTMR is enabled, you must alter CMR only if TCF = 1." Is this accounted for in your PR.

Yeah, this is the reason I did not implement tickless mode in this driver when I originally submitted it (see 21806b5).

@yongxu-wang15 yongxu-wang15 force-pushed the NXP-support-lptmr-tickless-function branch from 099ead3 to 6719da2 Compare October 16, 2025 08:32
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Hi @mmahadevan108 , I have added disable/start code logic in LPTMR_SetTimerPeriod to avoid the hardware limitations, tested passed on imx95 m7 power_mgmt_soc test case, the time sleep and tick record is right in my side, please help reivew it when you time free, thanks

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henrikbrixandersen requested changes Oct 16, 2025
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Stopping/starting the timer when setting a new timeout will affect the ticks (as the time all the instructions between stopping and starting will not be counted). I don't think this is an acceptable solution.

@yongxu-wang15 yongxu-wang15 force-pushed the NXP-support-lptmr-tickless-function branch from 6719da2 to 2446f3e Compare October 17, 2025 08:46
@yongxu-wang15
dts: arm: nxp: imx95_m7: add lptmr1 node
78e58d2 
add lptmr1 node into imx95 m7 dts which locate on Always On
domain and can continue work when whole soc enter system sleep mode

Signed-off-by: Yongxu Wang <[email protected]>
@yongxu-wang15
board: nxp: imx95_evk_mimx9596_m7: set lptmr1 interface
8d5ffa7 
remove lptmr2 and enable lptmr1 interface as default

Signed-off-by: Yongxu Wang <[email protected]>
@yongxu-wang15
test: counter_basic_api: add imx95 evk m7 support
ca7d1ea 
Enable lptmr interface to support counter_basic_api test case

Signed-off-by: Yongxu Wang <[email protected]>
@yongxu-wang15
soc: nxp: imx95: use lptmr if enabled PM
a838480 
Use lptmr interface as system clock if enabled PM
as system tick can't continue work in system suspend mode

Signed-off-by: Yongxu Wang <[email protected]>
@yongxu-wang15
drivers: mcux_lptmr_timer: support tickless function
5caaa07 
When tickless is enabled, it is necessary to ensure
that lptmr can be set for a period of time instead of
generating an interrupt at one tick

Set lptmr to the free running mode to ensure that
the current cycles value of lptmr can be directly obtained in ISR

Signed-off-by: Yongxu Wang <[email protected]>
@yongxu-wang15 yongxu-wang15 force-pushed the NXP-support-lptmr-tickless-function branch from 2446f3e to ac6e777 Compare October 17, 2025 08:56
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Hi @henrikbrixandersen I fully understand your concerns. After reconfirming with the design team, we need to ensure that there is sufficient time when updating the CMP. We can choose to reset(but this will cause the time to go back instead of monotonically increasing. Even through software, it is difficult to guarantee that there are no corner cases). In the latest commit, I added a protection mechanism. When the distance is very close, It will postpone a windo to prevent it from being triggered. Of course, this should depend on different SoCs, please help review it again when you time free, thanks a lot

@yongxu-wang15
drivers: mcux_lptmr_timer: Add safety window for CMR updates
43ce283 
Add safety window mechanism to prevent race conditions when updating
LPTMR compare register (CMR).

Problem:
- Setting CMR too close to current hardware counter can cause missed
  interrupts and system hangs

Solution:
- Implement lptmr_set_safe_immediate() with configurable safety window

Signed-off-by: Yongxu Wang <[email protected]>
@yongxu-wang15 yongxu-wang15 force-pushed the NXP-support-lptmr-tickless-function branch from ac6e777 to 43ce283 Compare October 17, 2025 09:04
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Quality Gate Passed Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

@henrikbrixandersen
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Hi @henrikbrixandersen I fully understand your concerns. After reconfirming with the design team, we need to ensure that there is sufficient time when updating the CMP. We can choose to reset(but this will cause the time to go back instead of monotonically increasing. Even through software, it is difficult to guarantee that there are no corner cases). In the latest commit, I added a protection mechanism. When the distance is very close, It will postpone a windo to prevent it from being triggered. Of course, this should depend on different SoCs, please help review it again when you time free, thanks a lot

I'd like to hear @andyross and @teburd (System timer maintainer/collaborator) view on this. I am unsure if this is a good solution.

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area: Boards/SoCs area: Counter area: Tests Issues related to a particular existing or missing test area: Timer Timer platform: NXP Drivers NXP Semiconductors, drivers platform: NXP MPU platform: NXP NXP

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