Add frdm_mcxe31b board basic support

modules/hal_nxp/mcux/Kconfig.mcux

@@ -8,7 +8,8 @@ config HAS_MCUX
 	bool
 	depends on SOC_FAMILY_KINETIS || SOC_FAMILY_NXP_IMX || SOC_FAMILY_LPC || \
 		SOC_FAMILY_NXP_S32 || SOC_FAMILY_NXP_IMXRT || SOC_FAMILY_NXP_RW || \
-		SOC_FAMILY_MCXN || SOC_FAMILY_MCXA || SOC_FAMILY_MCXW || SOC_FAMILY_MCXC
+		SOC_FAMILY_MCXN || SOC_FAMILY_MCXA || SOC_FAMILY_MCXW || SOC_FAMILY_MCXC || \
+		SOC_FAMILY_MCXE
 
 if	HAS_MCUX
 

soc/nxp/mcx/mcxe/CMakeLists.txt

@@ -0,0 +1,4 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${SOC_SERIES})

soc/nxp/mcx/mcxe/Kconfig

@@ -0,0 +1,8 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_MCXE
+
+rsource "*/Kconfig"
+
+endif #SOC_FAMILY_MCXE

soc/nxp/mcx/mcxe/Kconfig.defconfig

@@ -0,0 +1,8 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_MCXE
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_MCXE

soc/nxp/mcx/mcxe/Kconfig.soc

@@ -0,0 +1,10 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_MCXE
+	bool
+
+config SOC_FAMILY
+	default "mcxe" if SOC_FAMILY_MCXE
+
+rsource "*/Kconfig.soc"

soc/nxp/mcx/mcxe/mcxe31x/CMakeLists.txt

@@ -0,0 +1,16 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(soc.c)
+zephyr_sources(sram_config.c)
+zephyr_include_directories(.)
+
+zephyr_library_sources_ifdef(CONFIG_SOC_RESET_HOOK mcxe31x_soc_initialization.S)
+
+zephyr_linker_sources_ifdef(CONFIG_BOARD_NXP_MCXE31X_BOOT_HEADER
+  ROM_START SORT_KEY 0 boot_header.ld)
+
+zephyr_linker_sources(SECTIONS itcm.ld)
+zephyr_code_relocate(FILES sram_config.c LOCATION ${CONFIG_SRAM_CONFIG_RELOCATE_MEM}_TEXT)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/nxp/mcx/mcxe/mcxe31x/Kconfig

@@ -0,0 +1,50 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_MCXE31X
+	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
+	select ARM
+	select CLOCK_CONTROL
+	select HAS_MCUX
+	select CPU_HAS_ICACHE
+	select CPU_HAS_DCACHE
+	select SOC_RESET_HOOK
+	select SOC_EARLY_INIT_HOOK
+	select CODE_DATA_RELOCATION
+
+if SOC_SERIES_MCXE31X
+
+if CODE_DATA_RELOCATION
+
+config SRAM_CONFIG_RELOCATE_MEM
+	string
+	default "ITCM"
+	help
+	  Select memory to relocate sram_config.c code
+
+endif # CODE_DATA_RELOCATION
+
+if BOARD_NXP_MCXE31X_BOOT_HEADER
+
+config BOOT_HEADER_OFFSET
+	hex "Flash config data offset"
+	default 0x0
+	help
+	  The flash config offset provides the boot ROM with the on-board
+	  flash type and parameters. The boot ROM requires a fixed flash config
+	  offset for FlexSPI device.
+
+config IMAGE_VECTOR_TABLE_OFFSET
+	hex "Image vector table offset"
+	default 0x1000
+	help
+	  The Image Vector Table (IVT) provides the boot ROM with pointers to
+	  the application entry point and device configuration data. The boot
+	  ROM requires a fixed IVT offset for each type of boot device.
+
+endif # BOARD_NXP_MCXE31X_BOOT_HEADER
+
+endif # SOC_SERIES_MCXE31X

soc/nxp/mcx/mcxe/mcxe31x/Kconfig.defconfig

@@ -0,0 +1,18 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_MCXE31X
+
+config NUM_IRQS
+	default 240
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CORTEX_M_SYSTICK
+
+config CORTEX_M_SYSTICK
+	default n if (MCUX_LPTMR_TIMER || MCUX_OS_TIMER)
+
+config ROM_START_OFFSET
+	default 0x1000
+
+endif # SOC_SERIES_MCXE31X

soc/nxp/mcx/mcxe/mcxe31x/Kconfig.soc

@@ -0,0 +1,68 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_MCXE31X
+	bool
+	select SOC_FAMILY_MCXE
+
+config SOC_SERIES
+	default "mcxe31x" if SOC_SERIES_MCXE31X
+
+config SOC_MCXE315
+	bool
+	select SOC_SERIES_MCXE31X
+
+config SOC_MCXE316
+	bool
+	select SOC_SERIES_MCXE31X
+
+config SOC_MCXE317
+	bool
+	select SOC_SERIES_MCXE31X
+
+config SOC_MCXE31B
+	bool
+	select SOC_SERIES_MCXE31X
+
+config SOC
+	default "mcxe315" if SOC_MCXE315
+	default "mcxe316" if SOC_MCXE316
+	default "mcxe317" if SOC_MCXE317
+	default "mcxe31b" if SOC_MCXE31B
+
+config SOC_PART_NUMBER_MCXE315MLF
+	bool
+	select SOC_MCXE315
+
+config SOC_PART_NUMBER_MCXE315MPA
+	bool
+	select SOC_MCXE315
+
+config SOC_PART_NUMBER_MCXE316MLF
+	bool
+	select SOC_MCXE316
+
+config SOC_PART_NUMBER_MCXE316MPA
+	bool
+	select SOC_MCXE316
+
+config SOC_PART_NUMBER_MCXE317MPA
+	bool
+	select SOC_MCXE317
+
+config SOC_PART_NUMBER_MCXE317MPB
+	bool
+	select SOC_MCXE317
+
+config SOC_PART_NUMBER_MCXE31BMPB
+	bool
+	select SOC_MCXE31B
+
+config SOC_PART_NUMBER
+	default "MCXE315MLF" if SOC_PART_NUMBER_MCXE315MLF
+	default "MCXE315MPA" if SOC_PART_NUMBER_MCXE315MPA
+	default "MCXE316MLF" if SOC_PART_NUMBER_MCXE316MLF
+	default "MCXE316MPA" if SOC_PART_NUMBER_MCXE316MPA
+	default "MCXE317MPA" if SOC_PART_NUMBER_MCXE317MPA
+	default "MCXE317MPB" if SOC_PART_NUMBER_MCXE317MPB
+	default "MCXE31BMPB" if SOC_PART_NUMBER_MCXE31BMPB

soc/nxp/mcx/mcxe/mcxe31x/boot_header.ld

@@ -0,0 +1,8 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+. += CONFIG_BOOT_HEADER_OFFSET - (. - __rom_start_address);
+KEEP(*(.boot_header))

soc/nxp/mcx/mcxe/mcxe31x/itcm.ld

@@ -0,0 +1,13 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+SECTION_PROLOGUE(.itcm_text,,)
+{
+    . = ALIGN(4);
+    _itcm_text_start = .;
+    KEEP(*(.itcm_text))
+    _itcm_text_end = .;
+} GROUP_LINK_IN(ITCM)

soc/nxp/mcx/mcxe/mcxe31x/mcxe31x_soc_initialization.S

@@ -0,0 +1,115 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/toolchain.h>
+#include <zephyr/linker/sections.h>
+
+#define MC_RGM_BASE DT_REG_ADDR(DT_NODELABEL(mc_rgm))
+#define MC_RGM_DES  0x0
+#define MC_RGM_FES  0x8
+
+_ASM_FILE_PROLOGUE
+
+GTEXT(soc_reset_hook)
+
+SECTION_FUNC(TEXT, soc_reset_hook)
+
+	/*
+	 * On destructive reset, SRAM and TCM memories must be initialized to a known value using a
+	 * 64-bit master before 32-bit masters can read or write to them. Note that SRAM retains
+	 * content during functional reset through a hardware mechanism, therefore accesses do not
+	 * cause any content corruption errors.
+	 *
+	 * This is implemented directly in ASM, to ensure no stack access is performed.
+	 */
+
+	/* If we come from a destructive reset, then ignore functional reset flags */
+	ldr r1, =MC_RGM_BASE
+	ldr r2, [r1, MC_RGM_DES]
+	cmp r2, 0x0
+	bne ECC_INIT
+	ldr r2, [r1, MC_RGM_FES]
+	cmp r2, 0x0
+	bne ECC_END
+
+ECC_INIT:
+	ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
+	ldr r2, = DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
+
+	subs	r2, #1
+
+	ble SRAM_LOOP_END
+
+	movs	r0, 0
+	movs	r3, 0
+
+SRAM_LOOP:
+	stm r1!, {r0,r3}
+	subs r2, 8
+	bge SRAM_LOOP
+
+SRAM_LOOP_END:
+
+#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
+
+	ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_itcm))
+	ldr r2, = DT_REG_SIZE(DT_CHOSEN(zephyr_itcm))
+
+	subs	r2, #1
+
+ITCM_LOOP:
+	stm r1!, {r0,r3}
+	subs r2, 8
+	bge ITCM_LOOP
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
+
+	ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_dtcm))
+	ldr r2, = DT_REG_SIZE(DT_CHOSEN(zephyr_dtcm))
+
+	subs	r2, #1
+
+DTCM_LOOP:
+	stm r1!, {r0,r3}
+	subs r2, 8
+	bge DTCM_LOOP
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(itcm1), okay)
+
+	ldr r1, = DT_REG_ADDR(DT_NODELABEL(itcm1))
+	ldr r2, = DT_REG_SIZE(DT_NODELABEL(itcm1))
+
+	subs	r2, #1
+
+ITCM1_LOOP:
+	stm r1!, {r0,r3}
+	subs r2, 8
+	bge ITCM1_LOOP
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(dtcm1), okay)
+
+	ldr r1, = DT_REG_ADDR(DT_NODELABEL(dtcm1))
+	ldr r2, = DT_REG_SIZE(DT_NODELABEL(dtcm1))
+
+	subs	r2, #1
+
+DTCM1_LOOP:
+	stm r1!, {r0,r3}
+	subs r2, 8
+	bge DTCM1_LOOP
+#endif
+
+ECC_END:
+	/* save lr value to r4 */
+	mov r4, lr
+	/* Jump to SystemInit function*/
+	bl SystemInit
+	mov lr, r4
+	bx lr

soc/nxp/mcx/mcxe/mcxe31x/pinctrl_soc.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_NXP_MCXE31X_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_NXP_MCXE31X_PINCTRL_SOC_H_
+
+#include <zephyr/drivers/pinctrl/pinctrl_nxp_siul2_common.h>
+#include <zephyr/dt-bindings/pinctrl/nxp-siul2-pinctrl.h>
+#include <zephyr/sys/util.h>
+
+#define NXP_SIUL2_PINMUX_INIT(group, value)                                            \
+	.mscr = {.inst = NXP_SIUL2_PINMUX_GET_MSCR_SIUL2_IDX(value),                       \
+		 .idx = NXP_SIUL2_PINMUX_GET_MSCR_IDX(value),                                  \
+		 .val = SIUL2_MSCR_SSS(NXP_SIUL2_PINMUX_GET_MSCR_SSS(value)) |                 \
+			SIUL2_MSCR_OBE(DT_PROP(group, output_enable)) |                            \
+			SIUL2_MSCR_IBE(DT_PROP(group, input_enable)) |                             \
+			SIUL2_MSCR_PUE(DT_PROP(group, bias_pull_up) ||                             \
+							DT_PROP(group, bias_pull_down)) |          \
+			SIUL2_MSCR_PUS(DT_PROP(group, bias_pull_up)) |                             \
+			SIUL2_MSCR_SRC(DT_ENUM_IDX(group, slew_rate)) |                            \
+			SIUL2_MSCR_DSE(DT_PROP(group, nxp_drive_strength)) |                       \
+			SIUL2_MSCR_INV(DT_PROP(group, nxp_invert))},                               \
+	.imcr = {                                                                          \
+		.inst = NXP_SIUL2_PINMUX_GET_IMCR_SIUL2_IDX(value),                            \
+		.idx = NXP_SIUL2_PINMUX_GET_IMCR_IDX(value),                                   \
+		.val = SIUL2_IMCR_SSS(NXP_SIUL2_PINMUX_GET_IMCR_SSS(value)),                   \
+	}
+
+#endif /* ZEPHYR_SOC_NXP_MCXE31X_PINCTRL_SOC_H_ */