st: wba65: add stm32wba65i_dk1 board, 'ns' variant for dk1 and nucleo boards

boards/st/nucleo_wba65ri/board.cmake

@@ -1,6 +1,29 @@
+# Copyright (c) 2025 STMicroelectronics
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+if(CONFIG_BUILD_WITH_TFM)
+  set(FLASH_BASE_ADDRESS_S 0x0C000000)
+
+  # Flash merged TF-M + Zephyr binary
+  set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex)
+
+  if(CONFIG_HAS_FLASH_LOAD_OFFSET)
+    MATH(EXPR TFM_HEX_BASE_ADDRESS_NS "${FLASH_BASE_ADDRESS_S}+${CONFIG_FLASH_LOAD_OFFSET}")
+  else()
+    set(TFM_HEX_BASE_ADDRESS_NS ${TFM_FLASH_BASE_ADDRESS_S})
+  endif()
+
+  # System entry point is TF-M vector, located 1kByte after tfm_fmw_partition in DTS
+  dt_nodelabel(tfm_partition_path NODELABEL slot0_secure_partition REQUIRED)
+  dt_reg_addr(tfm_partition_offset PATH ${tfm_partition_path} REQUIRED)
+  math(EXPR tfm_fwm_boot_address "${tfm_partition_offset}+${FLASH_BASE_ADDRESS_S}+0x400")
+
+  board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw"
+    "--erase" "--start-address=${tfm_fwm_boot_address}"
+  )
+else()
+  board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+endif()
 
 include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd-stm32.board.cmake)

boards/st/nucleo_wba65ri/board.yml

@@ -4,3 +4,5 @@ board:
   vendor: st
   socs:
     - name: stm32wba65xx
+      variants:
+        - name: ns

boards/st/nucleo_wba65ri/doc/nucleo_wba65ri.rst → boards/st/nucleo_wba65ri/doc/index.rst

@@ -3,23 +3,24 @@
 Overview
 ********
 
-NUCLEO-WBA65RI is a Bluetooth® Low Energy, 802.15.4 and Zigbee® wireless
-and ultra-low-power board embedding a powerful and ultra-low-power radio
-compliant with the Bluetooth® Low Energy SIG specification v5.4
-with IEEE 802.15.4-2015 and Zigbee® specifications.
+NUCLEO-WBA65RI is a Bluetooth |reg| Low Energy, 802.15.4 and Zigbee |reg|
+wireless and ultra-low-power board embedding a powerful and ultra-low-power
+radio compliant with the Bluetooth |reg| Low Energy SIG specification v5.4
+with IEEE 802.15.4-2015 and Zigbee |reg| specifications.
 
-The ARDUINO® Uno V3 connectivity support and the ST morpho headers allow the
-easy expansion of the functionality of the STM32 Nucleo open development
+The ARDUINO |reg| Uno V3 connectivity support and the ST morpho headers allow
+the easy expansion of the functionality of the STM32 Nucleo open development
 platform with a wide choice of specialized shields.
 
-- Ultra-low-power wireless STM32WBA65RI microcontroller based on the Arm®
-  Cortex®‑M33 core, featuring 2 Mbyte of flash memory and 512 Kbytes of SRAM in
-  a VFQFPN68 package
+- Ultra-low-power wireless STM32WBA65RI microcontroller based on the Arm |reg|
+  Cortex |reg| ‑M33 core with TrustZone |reg|, MPU, DSP, and FPU, that operates
+  at a frequency of up to 100 MHz, featuring 2 Mbyte of flash memory and 512
+  Kbytes of SRAM in a VFQFPN68 package
 
 - MCU RF board (MB2130):
 
-  - 2.4 GHz RF transceiver supporting Bluetooth® specification v5.4
-  - Arm® Cortex® M33 CPU with TrustZone®, MPU, DSP, and FPU
+  - 2.4 GHz RF transceiver supporting Bluetooth |reg| specification v5.4
+  - Arm |reg| Cortex |reg| M33 CPU with TrustZone |reg|, MPU, DSP, and FPU
   - Integrated PCB antenna
 
 - Three user LEDs
@@ -28,7 +29,7 @@ platform with a wide choice of specialized shields.
 - Board connectors:
 
   - 2 USB Type-C
-  - ARDUINO® Uno V3 expansion connector
+  - ARDUINO |reg| Uno V3 expansion connector
   - ST morpho headers for full access to all STM32 I/Os
 
 - Flexible power-supply options: ST-LINK USB VBUS or external sources
@@ -39,19 +40,18 @@ Hardware
 ********
 
 The STM32WBA65xx multiprotocol wireless and ultralow power devices embed a
-powerful and ultralow power radio compliant with the Bluetooth® SIG Low Energy
-specification 5.4. They contain a high-performance Arm Cortex-M33 32-bit RISC
-core. They operate at a frequency of up to 100 MHz.
+powerful and ultralow power radio compliant with the Bluetooth |reg| SIG Low
+Energy specification 5.4.
 
 - Includes ST state-of-the-art patented technology
 
 - Ultra low power radio:
 
   - 2.4 GHz radio
-  - RF transceiver supporting Bluetooth® Low Energy 5.4 specification
-    IEEE 802.15.4-2015 PHY and MAC, supporting Thread, Matter and Zigbee®
+  - RF transceiver supporting Bluetooth |reg| Low Energy 5.4 specification
+    IEEE 802.15.4-2015 PHY and MAC, supporting Thread, Matter and Zigbee |reg|
   - Proprietary protocols
-  - RX sensitivity: -96 dBm (Bluetooth® Low Energy at 1 Mbps)
+  - RX sensitivity: -96 dBm (Bluetooth |reg| Low Energy at 1 Mbps)
     and -100 dBm (IEEE 802.15.4 at 250 kbps)
   - Programmable output power, up to +10 dBm with 1 dB steps
   - Support for external PA
@@ -64,23 +64,21 @@ core. They operate at a frequency of up to 100 MHz.
   - 1.71 to 3.6 V power supply
   - - 40 °C to 85 °C temperature range
   - Autonomous peripherals with DMA, functional down to Stop 1 mode
-  - TBD nA Standby mode (16 wake-up pins)
-  - TBD nA Standby mode with RTC
-  - TBD µA Standby mode with 64 KB SRAM
-  - TBD µA Stop 2 mode with 64 KB SRAM
-  - TBD µA/MHz Run mode at 3.3 V
-  - Radio: Rx TBD mA / Tx at 0 dBm TBD mA
-
-- Core: Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, and FPU
-- ART Accelerator™: 8-Kbyte instruction cache allowing 0-wait-state execution
+  - 120 nA Standby mode (16 wake-up pins)
+  - 1.68 |micro| A Standby mode with 64 KB SRAM with RTC
+  - 5.58 |micro| A Stop 2 mode with 64 KB SRAM with RTC
+  - 28.75 |micro| A/MHz Run mode at 3.3 V
+  - Radio: Rx 4.26 mA / Tx at 0 dBm 5.94 mA
+
+- ART Accelerator |trade|: 8-Kbyte instruction cache allowing 0-wait-state execution
   from flash memory (frequency up to 100 MHz, 150 DMIPS)
 - Power management: embedded regulator LDO and SMPS step-down converter
 - Supporting switch on-the-fly and voltage scaling
 
 - Benchmarks:
 
   - 1.5 DMIPS/MHz (Drystone 2.1)
-  - 410 CoreMark® (4.10 CoreMark/MHz)
+  - 410 CoreMark |reg| (4.10 CoreMark/MHz)
 
 - Clock sources:
 
@@ -104,7 +102,7 @@ core. They operate at a frequency of up to 100 MHz.
 
   - Four UARTs (ISO 7816, IrDA, modem)
   - Three SPIs
-  - Four I2C Fm+ (1 Mbit/s), SMBus/PMBus®
+  - Four I2C Fm+ (1 Mbit/s), SMBus/PMBus |reg|
 
 - System peripherals:
 
@@ -121,7 +119,7 @@ core. They operate at a frequency of up to 100 MHz.
 
 - Security and cryptography:
 
-  - Arm® TrustZone® and securable I/Os, memories, and peripherals
+  - Arm |reg| TrustZone |reg| and securable I/Os, memories, and peripherals
   - Flexible life cycle scheme with RDP and password protected debug
   - Root of trust thanks to unique boot entry and secure hide protection area (HDP)
   - SFI (secure firmware installation) thanks to embedded RSS (root secure services)
@@ -139,7 +137,7 @@ core. They operate at a frequency of up to 100 MHz.
 
 - Development support:
 
-  - Serial wire debug (SWD), JTAG
+  - Serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade|
 
 - ECOPACK2 compliant package
 
@@ -165,6 +163,48 @@ To fetch Binary Blobs:
 
    west blobs fetch hal_stm32
 
+Zephyr board options
+====================
+
+Zephyr supports building both Secure and Non-Secure firmware for
+Nucleo WBA65RI board where TF-M is the embedded Secure firmware
+and Zephyr the Non-Secure firmware.
+
+The BOARD options are summarized below:
+
++---------------------------------+------------------------------------------+
+| BOARD                           | Description                              |
++=================================+==========================================+
+| stm32wba65i_dk1                 | For building TrustZone Disabled firmware |
++---------------------------------+------------------------------------------+
+| stm32wba65i_dk1/stm32wba65xx/ns | For building Non-Secure firmware         |
++---------------------------------+------------------------------------------+
+
+Here are the instructions to build Zephyr with a non-secure configuration,
+using :zephyr:code-sample:`tfm_ipc` sample:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/tfm_integration/tfm_ipc
+   :board: nucleo_wba65ri/stm32wba65xx/ns
+   :goals: build
+
+Once done, before flashing, you need to first run a generated script that
+will set platform Option Bytes config and erase internal flash (among others,
+Option Bit TZEN will be set).
+
+.. code-block:: bash
+
+   $ ./build/tfm/api_ns/regression.sh
+   $ west flash
+
+Please note that, after having programmed the board for a TrustZone enabled system
+(e.g. with ``./build/tfm/api_ns/regression.sh``), the SoC TZEN Option Byte is enabled
+and you will need to operate specific sequence to disable this TZEN Option Byte
+configuration to get your board back in normal state for booting with a TrustZone
+disabled system (e.g. without TF-M support).
+You can use STM32CubeProgrammer_ to disable the SoC TZEN Option Byte config. Refer
+to `How to disable STM32WBA65 TZEN Option Byte`_.
+
 Connections and IOs
 ===================
 
@@ -213,7 +253,7 @@ Flashing
 The board is configured to be flashed using west `STM32CubeProgrammer`_ runner,
 so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required.
 
-Alternatively, openocd can also be used to flash the board using
+Alternatively, OpenOCD can also be used to flash the board using
 the ``--runner`` (or ``-r``) option:
 
 .. code-block:: console
@@ -252,3 +292,6 @@ You can debug an application in the usual way using OpenOCD. Here is an example
 
 .. _STM32CubeProgrammer:
    https://www.st.com/en/development-tools/stm32cubeprog.html
+
+.. _How to disable STM32WBA65 TZEN Option Byte:
+   https://wiki.st.com/stm32mcu/wiki/Connectivity:STM32WBA_BLE_%26_TrustZone#How_to_disable_the_TrustZone

boards/st/nucleo_wba65ri/nucleo_wba65ri_stm32wba65xx_ns.dts

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include "nucleo_wba65ri.dts"
+
+/ {
+	chosen {
+		zephyr,code-partition = &slot0_ns_partition;
+	};
+
+	/* SRAM1 (node label sram0) last 64kByte are owned by TF-M */
+	memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(448 - 64)>;
+	};
+
+	/* SRAM2 (node label sram1) is owned by TF-M */
+	/delete-node/ memory@20070000;
+};
+
+
+&flash0 {
+	/delete-node/ partitions;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "bootstage";
+			reg = <0 DT_SIZE_K(48)>;
+		};
+
+		slot0_secure_partition: partition@c000 {
+			label = "image-secure";
+			reg = <0xc000 DT_SIZE_K(256)>;
+		};
+
+		slot0_ns_partition: partition@4c000 {
+			label = "image-non-secure";
+			reg = <0x4c000 DT_SIZE_K(512)>;
+		};
+
+		storage_partition: partition@cc000 {
+			label = "storage";
+			reg = <0xcc000 (DT_SIZE_M(2) - DT_SIZE_K(48 + 256 + 512))>;
+		};
+	};
+};

boards/st/nucleo_wba65ri/nucleo_wba65ri_stm32wba65xx_ns.yaml

@@ -0,0 +1,10 @@
+identifier: nucleo_wba65ri/stm32wba65xx/ns
+name: ST Nucleo WBA65RI with TF-M and non-secure firmware
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 384
+flash: 512
+vendor: st

boards/st/nucleo_wba65ri/nucleo_wba65ri_stm32wba65xx_ns_defconfig

@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2025 STMicroelectronics
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable the internal SMPS regulator
+CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
+
+# Header offset since TF-M has no BL2 hence Zephyr is not signed
+CONFIG_ROM_START_OFFSET=0x400
+
+# Enable TZ non-secure configuration
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y
+CONFIG_RUNTIME_NMI=y

boards/st/stm32wba65i_dk1/Kconfig.defconfig

@@ -0,0 +1,13 @@
+# STM32WBA65I Discovery kit board configuration
+
+# Copyright (c) 2025 STMicroelectronics
+
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_STM32WBA65I_DK1
+
+config SPI_STM32_INTERRUPT
+	default y
+	depends on SPI
+
+endif # BOARD_STM32WBA65I_DK1

boards/st/stm32wba65i_dk1/Kconfig.stm32wba65i_dk1

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_STM32WBA65I_DK1
+	select SOC_STM32WBA65XX

boards/st/stm32wba65i_dk1/arduino_r3_connector.dtsi

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/arduino-header-r3.h>
+
+/ {
+	arduino_header: connector {
+		compatible = "arduino-header-r3";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <ARDUINO_HEADER_R3_A0 0 &gpioa 4 0>,
+			   <ARDUINO_HEADER_R3_A1 0 &gpioa 6 0>,
+			   <ARDUINO_HEADER_R3_A2 0 &gpioa 2 0>,
+			   <ARDUINO_HEADER_R3_A3 0 &gpioa 1 0>,
+			   <ARDUINO_HEADER_R3_A4 0 &gpioa 5 0>,
+			   <ARDUINO_HEADER_R3_A5 0 &gpioa 0 0>,
+			   <ARDUINO_HEADER_R3_D0 0 &gpioa 11 0>,
+			   <ARDUINO_HEADER_R3_D1 0 &gpioa 12 0>,
+			   <ARDUINO_HEADER_R3_D2 0 &gpioe 0 0>,
+			   <ARDUINO_HEADER_R3_D3 0 &gpiob 13 0>,
+			   <ARDUINO_HEADER_R3_D4 0 &gpioa 3 0>,
+			   <ARDUINO_HEADER_R3_D5 0 &gpiob 14 0>,
+			   <ARDUINO_HEADER_R3_D6 0 &gpiob 0 0>,
+			   <ARDUINO_HEADER_R3_D7 0 &gpiod 14 0>,
+			   <ARDUINO_HEADER_R3_D8 0 &gpioa 10 0>,
+			   <ARDUINO_HEADER_R3_D9 0 &gpiob 11 0>,
+			   <ARDUINO_HEADER_R3_D10 0 &gpiob 9 0>,
+			   <ARDUINO_HEADER_R3_D11 0 &gpioc 3 0>,
+			   <ARDUINO_HEADER_R3_D12 0 &gpioa 9 0>,
+			   <ARDUINO_HEADER_R3_D13 0 &gpiob 10 0>,
+			   <ARDUINO_HEADER_R3_D14 0 &gpiob 1 0>,
+			   <ARDUINO_HEADER_R3_D15 0 &gpiob 2 0>;
+	};
+};
+
+arduino_i2c: &i2c1 {};
+arduino_spi: &spi1 {};