Add kit_pse84_eval basic board and functionality support

boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk.dts

@@ -39,8 +39,9 @@ uart3: &scb3 {
 
 &peri0_group4_8bit_0 {
 	status = "okay";
-	scb-block = <3>;
-	div-value = <109>;
+	resource-type = <IFX_RSC_SCB>;
+	resource-instance = <3>;
+	clock-div = <109>;
 };
 
 &path_mux0 {

boards/infineon/kit_psc3m5_evk/kit_psc3m5_evk_psc3m5fds2afq1_ns.dts

@@ -39,8 +39,9 @@ uart3: &scb3 {
 
 &peri0_group4_8bit_0 {
 	status = "okay";
-	scb-block = <3>;
-	div-value = <109>;
+	resource-type = <IFX_RSC_SCB>;
+	resource-instance = <3>;
+	clock-div = <109>;
 };
 
 &path_mux0 {

drivers/clock_control/CMakeLists.txt

@@ -27,9 +27,9 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF                 clock_cont
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION nrf_clock_calibration.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC          clock_control_rv32m1_pcc.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_INFINEON_CAT1       clock_control_ifx_cat1.c)
-zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT1_FIXED_CLOCK       clock_control_ifx_cat1_fixed_clock.c)
-zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT1_FIXED_FACTOR_CLOCK       clock_control_ifx_cat1_fixed_factor_clock.c)
-zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_CAT1_PERI_CLOCK       clock_control_ifx_cat1_peri_clock.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_FIXED_CLOCK       clock_control_ifx_fixed_clock.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_FIXED_FACTOR_CLOCK       clock_control_ifx_fixed_factor_clock.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IFX_PERI_CLOCK       clock_control_ifx_peri_clock.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAM                 clock_control_sam_pmc.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAMA7G5             clock_control_sama7g5_pmc.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAMA7G5             clock_control_sama7g5_sckc.c)

drivers/clock_control/Kconfig.ifx_cat1

@@ -12,26 +12,23 @@ config CLOCK_CONTROL_INFINEON_CAT1
 	help
 	  This option enables the clock control driver for Infineon CAT1 family.
 
-config CLOCK_CONTROL_IFX_CAT1_FIXED_CLOCK
+config CLOCK_CONTROL_IFX_FIXED_CLOCK
 	bool "Infineon CAT1 Fixed clock driver"
 	default y
-	depends on SOC_FAMILY_INFINEON_CAT1
 	depends on DT_HAS_INFINEON_FIXED_CLOCK_ENABLED
 	help
 	  This option enables the Fixed clock driver for Infineon CAT1 family.
 
-config CLOCK_CONTROL_IFX_CAT1_FIXED_FACTOR_CLOCK
+config CLOCK_CONTROL_IFX_FIXED_FACTOR_CLOCK
 	bool "Infineon CAT1 Fixed factor clock driver"
 	default y
-	depends on SOC_FAMILY_INFINEON_CAT1
 	depends on DT_HAS_INFINEON_FIXED_FACTOR_CLOCK_ENABLED
 	help
 	  This option enables the Fixed clock driver for Infineon CAT1 family.
 
-config CLOCK_CONTROL_IFX_CAT1_PERI_CLOCK
+config CLOCK_CONTROL_IFX_PERI_CLOCK
 	bool "Infineon CAT1 Fixed clock driver"
 	default y
-	depends on SOC_FAMILY_INFINEON_CAT1
-	depends on DT_HAS_INFINEON_CAT1_PERI_DIV_ENABLED
+	depends on DT_HAS_INFINEON_PERI_DIV_ENABLED
 	help
 	  This option enables the Peripheral clock driver for Infineon CAT1 family.

drivers/clock_control/clock_control_ifx_fixed_clock.c

@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Clock control driver for Infineon CAT1 MCU family.
+ */
+
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/kernel.h>
+#include <stdlib.h>
+
+#include <infineon_kconfig.h>
+#include <zephyr/drivers/clock_control/clock_control_ifx_cat1.h>
+#include <zephyr/dt-bindings/clock/ifx_clock_source_common.h>
+#include <zephyr/dt-bindings/clock/ifx_clock_source_boards.h>
+
+#include <cy_sysclk.h>
+
+#define DT_DRV_COMPAT infineon_fixed_clock
+
+struct fixed_rate_clock_config {
+	uint32_t rate;
+	uint32_t system_clock; /* ifx_cat1_clock_block */
+};
+
+__WEAK void ifx_clock_startup_error(uint32_t error)
+{
+	(void)error; /* Suppress the compiler warning */
+	while (1) {
+	}
+}
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dpll_hp))
+void ifx_clk_dpll_hp0_init(void)
+{
+#define CY_CFG_SYSCLK_PLL_ERROR 3
+
+	static cy_stc_dpll_hp_config_t dpll_hp_config = {
+		.pDiv = 0,
+		.nDiv = 15,
+		.kDiv = 1,
+		.nDivFract = 0,
+		.freqModeSel = CY_SYSCLK_DPLL_HP_CLK50MHZ_1US_CNT_VAL,
+		.ivrTrim = 0x8U,
+		.clkrSel = 0x1U,
+		.alphaCoarse = 0xCU,
+		.betaCoarse = 0x5U,
+		.flockThresh = 0x3U,
+		.flockWait = 0x6U,
+		.flockLkThres = 0x7U,
+		.flockLkWait = 0x4U,
+		.alphaExt = 0x14U,
+		.betaExt = 0x14U,
+		.lfEn = 0x1U,
+		.dcEn = 0x1U,
+		.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
+	};
+	static cy_stc_pll_manual_config_t dpll_config = {
+		.hpPllCfg = &dpll_hp_config,
+	};
+
+#if !defined(CY_PDL_TZ_ENABLED)
+	if (Cy_SysClk_PllIsEnabled(SRSS_DPLL_HP_0_PATH_NUM)) {
+		return;
+	}
+#endif
+	Cy_SysClk_PllDisable(SRSS_DPLL_HP_0_PATH_NUM);
+	if (CY_SYSCLK_SUCCESS !=
+	    Cy_SysClk_PllManualConfigure(SRSS_DPLL_HP_0_PATH_NUM, &dpll_config)) {
+		ifx_clock_startup_error(CY_CFG_SYSCLK_PLL_ERROR);
+	}
+	if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(SRSS_DPLL_HP_0_PATH_NUM, 10000u)) {
+		ifx_clock_startup_error(CY_CFG_SYSCLK_PLL_ERROR);
+	}
+}
+#endif
+
+static int fixed_rate_clk_init(const struct device *dev)
+{
+	const struct fixed_rate_clock_config *const config = dev->config;
+
+	switch (config->system_clock) {
+
+	case IFX_IMO:
+		break;
+
+	case IFX_FLL:
+		break;
+
+	case IFX_IHO:
+		Cy_SysClk_IhoEnable();
+		break;
+
+	case IFX_PILO:
+		Cy_SysClk_PiloEnable();
+		break;
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dpll_hp))
+	case IFX_DPLL500:
+		ifx_clk_dpll_hp0_init();
+		SystemCoreClockUpdate();
+		break;
+#endif
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+#define FIXED_CLK_INIT(n)                                                                          \
+	static const struct fixed_rate_clock_config fixed_rate_clock_config_##n = {                \
+		.rate = DT_INST_PROP(n, clock_frequency),                                          \
+		.system_clock = DT_INST_PROP(n, system_clock),                                     \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(n, fixed_rate_clk_init, NULL, NULL, &fixed_rate_clock_config_##n,    \
+			      PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(FIXED_CLK_INIT)

drivers/clock_control/clock_control_ifx_cat1_fixed_factor_clock.c → drivers/clock_control/clock_control_ifx_fixed_factor_clock.c

@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2025 Cypress Semiconductor Corporation (an Infineon company) or
- * an affiliate of Cypress Semiconductor Corporation
+ * Copyright (c) 2025 Infineon Technologies AG,
+ * or an affiliate of Infineon Technologies AG.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,8 +13,11 @@
 #include <zephyr/kernel.h>
 #include <stdlib.h>
 
+#include <infineon_kconfig.h>
 #include <zephyr/drivers/clock_control/clock_control_ifx_cat1.h>
-#include <zephyr/dt-bindings/clock/ifx_clock_source_def.h>
+#include <zephyr/dt-bindings/clock/ifx_clock_source_common.h>
+#include <zephyr/dt-bindings/clock/ifx_clock_source_boards.h>
+
 #include <cy_sysclk.h>
 
 #define DT_DRV_COMPAT infineon_fixed_factor_clock
@@ -24,21 +27,33 @@ struct fixed_factor_clock_config {
 	uint32_t block; /* ifx_cat1_clock_block */
 	uint32_t instance;
 	uint32_t source_path;
-	uint32_t source_instance;
+	uint32_t source_block;
 };
 
 static int fixed_factor_clk_init(const struct device *dev)
 {
 	const struct fixed_factor_clock_config *const config = dev->config;
+	uint32_t source_instance;
+
+	switch (config->source_block) {
+
+	case IFX_DPLL250_1:
+		source_instance = 1;
+		break;
+
+	default:
+		source_instance = 0;
+		break;
+	}
 
 	switch (config->block) {
 
-	case IFX_CAT1_CLOCK_BLOCK_PATHMUX:
+	case IFX_PATHMUX:
 		Cy_SysClk_ClkPathSetSource(config->instance, config->source_path);
 		break;
 
-	case IFX_CAT1_CLOCK_BLOCK_HF:
-		Cy_SysClk_ClkHfSetSource(config->instance, config->source_instance);
+	case IFX_HF:
+		Cy_SysClk_ClkHfSetSource(config->instance, source_instance);
 		Cy_SysClk_ClkHfSetDivider(config->instance, config->divider);
 		Cy_SysClk_ClkHfEnable(config->instance);
 		break;
@@ -50,16 +65,16 @@ static int fixed_factor_clk_init(const struct device *dev)
 	return 0;
 }
 
-#define FIXED_CLK_INIT(idx)                                                                        \
-	static const struct fixed_factor_clock_config fixed_factor_clock_config_##idx = {          \
-		.divider = DT_INST_PROP_OR(idx, clock_divider, 1u),                                \
-		.block = DT_INST_PROP(idx, clock_block),                                           \
-		.instance = DT_INST_PROP(idx, clock_instance),                                     \
-		.source_path = DT_INST_PROP_OR(idx, source_path, 1u),                              \
-		.source_instance = DT_INST_PROP_BY_PHANDLE(idx, clocks, clock_instance),           \
+#define FIXED_CLK_INIT(n)                                                                          \
+	static const struct fixed_factor_clock_config fixed_factor_clock_config_##n = {            \
+		.divider = DT_INST_PROP_OR(n, clock_div, 1u),                                      \
+		.block = DT_INST_PROP(n, system_clock),                                            \
+		.instance = DT_INST_PROP(n, instance),                                             \
+		.source_path = DT_INST_PROP_OR(n, source_path, 1u),                                \
+		.source_block = DT_INST_PROP_BY_PHANDLE(n, clocks, system_clock),                  \
 	};                                                                                         \
-	DEVICE_DT_INST_DEFINE(idx, fixed_factor_clk_init, NULL, NULL,                              \
-			      &fixed_factor_clock_config_##idx, PRE_KERNEL_1,                      \
+	DEVICE_DT_INST_DEFINE(n, fixed_factor_clk_init, NULL, NULL,                                \
+			      &fixed_factor_clock_config_##n, PRE_KERNEL_1,                        \
 			      CONFIG_CLOCK_CONTROL_INIT_PRIORITY, NULL);
 
 DT_INST_FOREACH_STATUS_OKAY(FIXED_CLK_INIT)