logging: backend: swo: Fix SWO clock divider check #96020
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The TPIU->ACPR register is only 13 bits wide, so the maximum allowed SWO clock divider is 0x1FFF. Signed-off-by: Henrik Grunmach <[email protected]>
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The TPIU->ACPR register is only 13 bits wide, so the maximum allowed SWO clock divider is 0x1FFF. Update the validation to use 0x1FFF instead of 0xFFFF