xtensa: memory domains: reuse page tables until changes are made #96235
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This is on top of #93947 as that PR also changes a bit of page table code. |
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Adds snippets-text-sections.ld to linker scripts. So that the mem_map test can run on qemu_xtensa/dc233c/mmu. Signed-off-by: Daniel Leung <[email protected]>
The fields in macro should be done with both shift and mask values to make it clear. So amend some macros so that the presentation are unified for them. Signed-off-by: Daniel Leung <[email protected]>
This skips the redirection of backup attributes and ring via some SW field macros, and use the PTE bits directly. Should make it easier to decode what's going on. Signed-off-by: Daniel Leung <[email protected]>
Almost all page table entry (PTE) related macros are only used in one source file. These macros are considered the internal working of MMU. There is no need to expose them in header file for other to reference. So move them into the source file where it is only place they are used. Bonus is that we can shorten the macro names as they are now local to the file. Makes it easier to read, and few keystrokes to input. Signed-off-by: Daniel Leung <[email protected]>
Some macros for the page tables array are local to the file so there is no need to prefix them with XTENSA_. Simplify by removing the XTENSA_ prefix, and clairfy if needed. Signed-off-by: Daniel Leung <[email protected]>
In l2_page_table_unmap(), invalidating TLBs should be limited to the address and not the whole auto-refill TLBs. Also fix a bug where the EXEC bit should be determined from the L2 PTE and not the L1 PTE. Signed-off-by: Daniel Leung <[email protected]>
If the page tables are not cached, there is no need to do any cache ops to flush or invalidate the data in cache. So skip them if the page tables are not cached. Saves a few CPU cycles. Signed-off-by: Daniel Leung <[email protected]>
When adding new memory domains, we need to start from kernel page tables by duplicating them. However, there is no need to duplicate all in-use page tables as some memory regions remain unchanged. Fror example, hardware register region where only kernel has access does not need to be duplicated across all memory domains. The same L2 table can be used among them. This changes the L2 page table allocation to be copy-on-write where we only need to duplicate a L2 table if changes need to be made on it. Signed-off-by: Daniel Leung <[email protected]>
Adds function for app to obtain page table usage statistics, allowing fine tuning of numbers of L1 and L2 page table array. Signed-off-by: Daniel Leung <[email protected]>
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area: Xtensa
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This changes the page table duplication to be COW (copy-on-write) to conserve memory space. When a new memory domain is created, the old mechanism was to duplicate all currently being used kernel page tables. The newly duplicated tables would then be modified to accommodate the new memory domain and its memory partitions. This wastes quite a bit of memory space as some tables remain unchanged, for example, page table for hardware register access and kernel only pages. The changes here modifies this mechanism to reuse existing kernel page tables until modifications are needed. Then it makes a copy of the table, and changes applied to the duplicated table.