drivers: ethernet: xlnx_gem: obtain data bus width at run-time, remove parameter from DT #96364
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zephyrbot
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ClaCodes,
decsny,
henrikbrixandersen,
lmajewski,
maass-hamburg,
michalsimek and
pdgendt
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This pull request looks good to me. I verified it on the ZCU102 ZynqMP board, where dma_bus_width_def was correctly read from designcfg_debug5 reg and written to the nw_cfg register. Ethernet communication also worked as expected. |
michalsimek
previously approved these changes
Oct 3, 2025
This was referenced Oct 3, 2025
maass-hamburg
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Oct 8, 2025
This parameter no longer needs to be configured at the SoC level in the declarations of the GEM controller instances (used to require different values for the Zynq-7000 and the ZynqMP) as the value matching the current target SoC is now being read at run-time from a design configuration register. Signed-off-by: Immo Birnbaum <[email protected]>
Remove the obsolete DT parameter "amba-ahb-dbus-width" from all GEM controller instance declarations for both the Zynq-7000 and the ZynqMP. The value matching the current target SoC is now being read at run-time from a design configuration register Signed-off-by: Immo Birnbaum <[email protected]>
…gister Obtain the value for the AMBA AHB bus width (32 bit/64 bit/128 bit) from the design_cfg5 register at init-time rather than specifying it in the respective SoC's DT. Signed-off-by: Immo Birnbaum <[email protected]>
Added the removal of the 'amba-ahb-dbus-width' devicetree property from the binding of the Xilinx GEM Ethernet controller driver to the current migration guide. Signed-off-by: Immo Birnbaum <[email protected]>
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maass-hamburg
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michalsimek
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Remove the 'amba-ahb-dbus-width' DT parameter and obtain the matching value for the current target SoC at run-time during the device initialization. The matching value for the current SoC is available in the GEM register space's design_cfg5 register.