Add mcxa344 baseline support

boards/nxp/frdm_mcxa344/CMakeLists.txt

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+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+zephyr_library_sources(board.c)

boards/nxp/frdm_mcxa344/Kconfig

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+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_MCXA344
+	select BOARD_EARLY_INIT_HOOK

boards/nxp/frdm_mcxa344/Kconfig.frdm_mcxa344

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+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_MCXA344
+	select SOC_MCXA344
+	select SOC_PART_NUMBER_MCXA344VLL

boards/nxp/frdm_mcxa344/board.c

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+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/init.h>
+#include <zephyr/device.h>
+#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
+#include <fsl_clock.h>
+#include <fsl_spc.h>
+#include <soc.h>
+
+/* Core clock frequency: 180MHz */
+#define CLOCK_INIT_CORE_CLOCK               180000000U
+#define BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK 180000000U
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+void board_early_init_hook(void)
+{
+	uint32_t coreFreq;
+	spc_active_mode_core_ldo_option_t ldoOption;
+	spc_sram_voltage_config_t sramOption;
+
+	/* Get the CPU Core frequency */
+	coreFreq = CLOCK_GetCoreSysClkFreq();
+
+	/* The flow of increasing voltage and frequency */
+	if (coreFreq <= BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK) {
+		/* Set the LDO_CORE VDD regulator level */
+		ldoOption.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage;
+		ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+		(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+		/* Configure Flash to support different voltage level and frequency */
+		FMU0->FCTRL =
+			(FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x4U));
+		/* Specifies the operating voltage for the SRAM's read/write timing margin */
+		sramOption.operateVoltage = kSPC_sramOperateAt1P2V;
+		sramOption.requestVoltageUpdate = true;
+		(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+	}
+
+	/*!< Set up system dividers */
+	CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set SYSCON.AHBCLKDIV divider to value 1 */
+	CLOCK_SetClockDiv(kCLOCK_DivFRO_HF, 1U); /* !< Set SYSCON.FROHFDIV divider to value 1 */
+	CLOCK_SetupFROHFClocking(BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK); /*!< Enable FRO HF */
+	CLOCK_SetupFRO12MClocking();             /*!< Setup FRO12M clock */
+
+	CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to kFRO_HF */
+
+	/* The flow of decreasing voltage and frequency */
+	if (coreFreq > BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK) {
+		/* Configure Flash to support different voltage level and frequency */
+		FMU0->FCTRL =
+			(FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x4U));
+		/* Specifies the operating voltage for the SRAM's read/write timing margin */
+		sramOption.operateVoltage = kSPC_sramOperateAt1P2V;
+		sramOption.requestVoltageUpdate = true;
+		(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+		/* Set the LDO_CORE VDD regulator level */
+		ldoOption.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage;
+		ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+		(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+	}
+
+	/*!< Set up clock selectors - Attach clocks to the peripheries */
+	CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
+
+	/*!< Set up dividers */
+	CLOCK_SetClockDiv(kCLOCK_DivFRO_LF, 1U); /* !< Set SYSCON.FROLFDIV divider to value 1 */
+	CLOCK_SetClockDiv(kCLOCK_DivTRACE, 2U);  /* !< Set MRCC.TRACE_CLKDIV divider to value 2 */
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porta))
+	RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GatePORT0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portb))
+	RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GatePORT1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portc))
+	RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GatePORT2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portd))
+	RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GatePORT3);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porte))
+	RESET_ReleasePeripheralReset(kPORT4_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GatePORT4);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0))
+	RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
+	RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2))
+	RESET_ReleasePeripheralReset(kGPIO2_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3))
+	RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO3);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4))
+	RESET_ReleasePeripheralReset(kGPIO4_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO4);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+	CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART0);
+	RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART1, 1u);
+	CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART1);
+	RESET_ReleasePeripheralReset(kLPUART1_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart2))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART2, 1u);
+	CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART2);
+	RESET_ReleasePeripheralReset(kLPUART2_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart3))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART3, 1u);
+	CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART3);
+	RESET_ReleasePeripheralReset(kLPUART3_RST_SHIFT_RSTn);
+#endif
+
+	/* Set SystemCoreClock variable. */
+	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
+}

boards/nxp/frdm_mcxa344/board.cmake

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+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+board_runner_args(jlink "--device=MCXA344")
+board_runner_args(linkserver "--device=MCXA344:FRDM-MCXA344")
+board_runner_args(pyocd "--target=MCXA344")
+
+include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)

boards/nxp/frdm_mcxa344/board.yml

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+board:
+  name: frdm_mcxa344
+  full_name: FRDM-MCXA344
+  vendor: nxp
+  socs:
+  - name: mcxa344

boards/nxp/frdm_mcxa344/doc/index.rst

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+.. zephyr:board:: frdm_mcxa344
+
+Overview
+********
+
+The MCXA344 Mixed-Signal MCUs, featuring an Arm® Cortex®-M33, support running up to
+180 MHz, 256 KB Flash and 64 kB RAM. The MCX A344 targets motor control applications,
+optimized with high performance and MAU engine, integrated 2x FlexPWM with 4x submodule
+combined with AOI, up to 2x ADC and rich serial peripheral and SmartDMA. The MCX MCX-A344
+devices are supported by the MCUXpresso Developer Experience to optimize, ease and help
+accelerate embedded system development.
+
+Hardware
+********
+
+- MCX-A344 Arm Cortex-M33 microcontroller running at 180 MHz
+- 256KB dual-bank on chip Flash
+- 64 KB RAM
+- 1x FlexCAN with FD, 1x RGB LED, 3x SW buttons
+- On-board MCU-Link debugger with CMSIS-DAP
+- Arduino Header, SmartDMA/Camera Header, mikroBUS
+
+For more information about the MCX-A344 SoC and FRDM-MCXA344 board, see:
+
+- `MCX-A344 SoC Website`_
+- `MCX-A344 Datasheet`_
+- `MCX-A344 Reference Manual`_
+- `FRDM-MCXA344 Website`_
+- `FRDM-MCXA344 User Guide`_
+- `FRDM-MCXA344 Board User Manual`_
+- `FRDM-MCXA344 Schematics`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+The MCX-A344 SoC has 5 gpio controllers and has pinmux registers which
+can be used to configure the functionality of a pin.
+
++------------+-----------------+----------------------------+
+| Name       | Function        | Usage                      |
++============+=================+============================+
+| PIO2_3     | UART            | UART RX                    |
++------------+-----------------+----------------------------+
+| PIO2_2     | UART            | UART TX                    |
++------------+-----------------+----------------------------+
+
+System Clock
+============
+
+The MCX-A344 SoC is configured to use FRO running at 180MHz as a source for
+the system clock.
+
+Serial Port
+===========
+
+The FRDM-MCXA344 SoC has 4 LPUART  interfaces for serial communication.
+LPUART 2 is configured as UART for the console.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Configuring a Debug Probe
+=========================
+
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
+
+Using LinkServer
+----------------
+
+Linkserver is the default runner for this board, and supports the factory
+default MCU-Link firmware. Follow the instructions in
+:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
+firmware. This only needs to be done if the default onboard debug circuit
+firmware was changed. To put the board in ``ISP mode`` to program the firmware,
+short jumper JP4.
+
+Using J-Link
+------------
+
+There are two options. The onboard debug circuit can be updated with Segger
+J-Link firmware by following the instructions in
+:ref:`mcu-link-jlink-onboard-debug-probe`.
+To be able to program the firmware, you need to put the board in ``ISP mode``
+by shortening the jumper JP4.
+The second option is to attach a :ref:`jlink-external-debug-probe` to the
+10-pin SWD connector (J11) of the board. Additionally, the jumper JP6 must
+be shorted.
+For both options use the ``-r jlink`` option with west to use the jlink runner.
+
+.. code-block:: console
+
+   west flash -r jlink
+
+Configuring a Console
+=====================
+
+Connect a USB cable from your PC to J13, and use the serial terminal of your choice
+(minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Flashing
+========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: frdm_mcxa344
+   :goals: flash
+
+Open a serial terminal, reset the board (press the RESET button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
+   Hello World! frdm_mcxa344/mcxa344
+
+Debugging
+=========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: frdm_mcxa344/mcxa344
+   :goals: debug
+
+Open a serial terminal, step through the application in your debugger, and you
+should see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
+   Hello World! frdm_mcxa344/mcxa344
+
+Troubleshooting
+===============
+
+.. include:: ../../common/segger-ecc-systemview.rst
+   :start-after: segger-ecc-systemview
+
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
+.. _MCX-A344 SoC Website:
+   TBD
+
+.. _MCX-A344 Datasheet:
+   TBD
+
+.. _MCX-A344 Reference Manual:
+   TBD
+
+.. _FRDM-MCXA344 Website:
+   TBD
+
+.. _FRDM-MCXA344 User Guide:
+   TBD
+
+.. _FRDM-MCXA344 Board User Manual:
+   TBD
+
+.. _FRDM-MCXA344 Schematics:
+   TBD

boards/nxp/frdm_mcxa344/frdm_mcxa344-pinctrl.dtsi

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+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <nxp/mcx/MCXA344VLL-pinctrl.h>
+
+&pinctrl {
+	pinmux_lpuart2: pinmux_lpuart2 {
+		group0 {
+			pinmux = <LPUART2_RXD_P2_3>,
+				<LPUART2_TXD_P2_2>;
+			drive-strength = "low";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
+};