drivers: clock: SAM D5x/E5x: add more functionality

boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.dts

@@ -40,7 +40,82 @@
 };
 
 &cpu0 {
-	clock-frequency = <48000000>;
+	clock-frequency = <120000000>;
+};
+
+&clock {
+	compatible = "microchip,sam-d5x-e5x-clock";
+
+	xosc: xosc {
+		compatible = "microchip,sam-d5x-e5x-xosc";
+		xosc1 {
+			subsystem = <CLOCK_MCHP_XOSC_ID_XOSC1>;
+			xosc-frequency = <12000000>;
+			xosc-en = <1>;
+			xosc-xtal-en = <1>;
+			xosc-run-in-standby-en = <1>;
+		};
+	};
+
+	dfll: dfll {
+		compatible = "microchip,sam-d5x-e5x-dfll";
+		dfll-en = <0>;
+	};
+
+	fdpll: fdpll {
+		compatible = "microchip,sam-d5x-e5x-fdpll";
+		fdpll0 {
+			subsystem = <CLOCK_MCHP_FDPLL_ID_FDPLL0>;
+			fdpll-divider-ratio-int = <19>;
+			fdpll-lock-bypass-en = <1>;
+			fdpll-wakeup-fast-en = <1>;
+			fdpll-src = "xosc1";
+			fdpll-en = <1>;
+		};
+	};
+
+	xosc32k: xosc32k {
+		compatible = "microchip,sam-d5x-e5x-xosc32k";
+		xosc32k-xtal-en = <1>;
+		xosc32k-startup-time = <62>;
+		xosc32k-gain-mode = "standard";
+		xosc32k-en = <1>;
+		xosc32k-32khz-en = <1>;
+		xosc32k-1khz-en = <1>;
+	};
+
+	gclkgen: gclkgen {
+		compatible = "microchip,sam-d5x-e5x-gclkgen";
+
+		gclkgen0 {
+			subsystem = <CLOCK_MCHP_GCLKGEN_ID_GEN0>;
+			gclkgen-div-factor = <1>;
+			gclkgen-run-in-standby-en = <1>;
+			gclkgen-src = "fdpll0";
+			gclkgen-en = <1>;
+		};
+	};
+
+	gclkperiph: gclkperiph {
+		compatible = "microchip,sam-d5x-e5x-gclkperiph";
+		#clock-cells = <1>;
+
+		sercom2 {
+			subsystem = <CLOCK_MCHP_GCLKPERIPH_ID_SERCOM2_CORE>;
+			gclkperiph-src = "gclk0";
+			gclkperiph-en = <1>;
+		};
+	};
+
+	mclkperiph: mclkperiph {
+		compatible = "microchip,sam-d5x-e5x-mclkperiph";
+		#clock-cells = <1>;
+
+		sercom2 {
+			subsystem = <CLOCK_MCHP_MCLKPERIPH_ID_APBB_SERCOM2>;
+			mclk-en = <1>;
+		};
+	};
 };
 
 &sercom2 {

drivers/clock_control/Kconfig.mchp

@@ -16,11 +16,37 @@ config CLOCK_CONTROL_MCHP_SAM_D5X_E5X
 
 if CLOCK_CONTROL_MCHP_COMMON
 
+config CLOCK_CONTROL_MCHP_CONFIG_BOOTUP
+	bool "Bootup clock configuration"
+	default y
+	help
+	  This option enables bootup clock configuration from device tree node.
+
+config CLOCK_CONTROL_MCHP_CONFIG_RUNTIME
+	bool "Runtime clock configuration"
+	default y
+	help
+	  This option enables runtime clock configuration using API.
+
+config CLOCK_CONTROL_MCHP_ASYNC_ON
+	bool "Async clock on"
+	default n
+	help
+	  This option enables async on API.
+
 config CLOCK_CONTROL_MCHP_GET_RATE
 	bool "Get clock rate"
 	default y
 	help
 	  Enable support for retrieving the clock rate. This may increase
 	  code size, depending on the depth of clock source hierarchy.
 
+config CLOCK_CONTROL_MCHP_SET_RATE
+	bool "Set clock rate"
+	default n
+	depends on CLOCK_CONTROL_MCHP_GET_RATE
+	help
+	  This option enables set rate API. This may increase
+	  code size, depending on the depth of clock source hierarchy.
+
 endif # CLOCK_CONTROL_MCHP_COMMON