zephyrproject-rtos · nhutnguyenkc · Sep 29, 2025 · Sep 29, 2025 · Sep 29, 2025 · Sep 29, 2025
diff --git a/boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi b/boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi
@@ -32,4 +32,13 @@
 				 <RZV_PINMUX(PORT_18, 1, 3)>; /* SCL */
 		};
 	};
+
+	/omit-if-no-ref/ spi1_pins: spi1 {
+		spi1-pinmux {
+			pinmux = <RZV_PINMUX(PORT_44, 0, 1)>, /* CK */
+				 <RZV_PINMUX(PORT_44, 1, 1)>, /* MOSI */
+				 <RZV_PINMUX(PORT_44, 2, 1)>, /* MISO */
+				 <RZV_PINMUX(PORT_44, 3, 1)>; /* SSL */
+		};
+	};
 };
diff --git a/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.dts b/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.dts
@@ -43,3 +43,9 @@
 	pinctrl-names = "default";
 	status = "okay";
 };
+
+&spi1 {
+	pinctrl-0 = <&spi1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml b/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml
@@ -12,4 +12,5 @@ supported:
   - adc
   - i2c
   - mbox
+  - spi
 vendor: renesas
diff --git a/drivers/spi/spi_renesas_rz_rspi.c b/drivers/spi/spi_renesas_rz_rspi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -63,10 +63,10 @@ static bool spi_rz_rspi_transfer_ongoing(struct spi_rz_rspi_data *data)
 #if defined(CONFIG_SPI_RENESAS_RZ_RSPI_INTERRUPT)
 	return (spi_context_tx_on(&data->ctx) || spi_context_rx_on(&data->ctx));
 #else
-	if (spi_context_total_tx_len(&data->ctx) < spi_context_total_rx_len(&data->ctx)) {
-		return (spi_context_tx_on(&data->ctx) || spi_context_rx_on(&data->ctx));
-	} else {
+	if (spi_context_total_tx_len(&data->ctx) == spi_context_total_rx_len(&data->ctx)) {
 		return (spi_context_tx_on(&data->ctx) && spi_context_rx_on(&data->ctx));
+	} else {
+		return (spi_context_tx_on(&data->ctx) || spi_context_rx_on(&data->ctx));
 	}
 #endif
 }
@@ -263,6 +263,7 @@ static int spi_rz_rspi_transceive_data(struct spi_rz_rspi_data *data)
 {
 	R_RSPI0_Type *p_spi_reg = (R_RSPI0_Type *)data->fsp_ctrl->p_regs;
 	uint32_t data_count = (p_spi_reg->SPBFDR & R_RSPI0_SPBFDR_T_Msk) >> R_RSPI0_SPBFDR_T_Pos;
+	uint32_t rx;
 
 	data_count = 8 - data_count;
 
@@ -295,21 +296,28 @@ static int spi_rz_rspi_transceive_data(struct spi_rz_rspi_data *data)
 	spi_context_update_tx(&data->ctx, data->dfs, 1);
 
 	/* RX transfer */
-	if (spi_context_rx_on(&data->ctx)) {
+	while (!p_spi_reg->SPSR_b.SPRF) {
+	}
 
-		while (!p_spi_reg->SPSR_b.SPRF) {
-		}
+	if (data->dfs > 2) {
+		rx = (uint32_t)p_spi_reg->SPDR_b.SPD;
+	} else if (data->dfs > 1) {
+		rx = (uint16_t)p_spi_reg->SPDR_hword.L;
+	} else {
+		rx = (uint8_t)p_spi_reg->SPDR_byte.LL;
+	}
 
+	if (spi_context_rx_buf_on(&data->ctx)) {
 		/* Read data from Data Register */
 		if (data->dfs > 2) {
-			UNALIGNED_PUT(p_spi_reg->SPDR_b.SPD, (uint32_t *)data->ctx.rx_buf);
+			UNALIGNED_PUT(rx, (uint32_t *)data->ctx.rx_buf);
 		} else if (data->dfs > 1) {
-			UNALIGNED_PUT(p_spi_reg->SPDR_hword.L, (uint16_t *)data->ctx.rx_buf);
+			UNALIGNED_PUT(rx, (uint16_t *)data->ctx.rx_buf);
 		} else {
-			UNALIGNED_PUT(p_spi_reg->SPDR_byte.LL, (uint8_t *)data->ctx.rx_buf);
+			UNALIGNED_PUT(rx, (uint8_t *)data->ctx.rx_buf);
 		}
-		spi_context_update_rx(&data->ctx, data->dfs, 1);
 	}
+	spi_context_update_rx(&data->ctx, data->dfs, 1);
 	return 0;
 }
 #endif /* #if !defined(CONFIG_SPI_RENESAS_RZ_RSPI_INTERRUPT) */

diff --git a/dts/arm/renesas/rz/rzv/r9a07g054.dtsi b/dts/arm/renesas/rz/rzv/r9a07g054.dtsi
@@ -8,6 +8,7 @@
 #include <freq.h>
 #include <zephyr/dt-bindings/adc/adc.h>
 #include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/dma/renesas_rz_dma.h>
 
 / {
 	compatible = "renesas,r9a07g054";
@@ -507,6 +508,26 @@
 			};
 		};
 
+		dma0: dma@41800000 { /* Secure DMA */
+			compatible = "renesas,rz-dma";
+			reg = <0x41800000 0x800>, <0x41810000 0x20>;
+			reg-names = "reg_main", "ext";
+			interrupts = <108 1>, <109 1>, <110 1>, <111 1>,
+				     <112 1>, <113 1>, <114 1>, <115 1>,
+				     <116 1>, <117 1>, <118 1>, <119 1>,
+				     <120 1>, <121 1>, <122 1>, <123 1>,
+				     <124 1>; /* DMAERR1 */
+			interrupt-names = "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15",
+					  "err1";
+			dma-channels = <16>;
+			#dma-cells = <2>;
+			dma-buf-addr-alignment = <4>;
+			status = "disabled";
+		};
+
 		scif0: serial@4004b800 {
 			compatible = "renesas,rz-scif-uart";
 			channel = <0>;
@@ -925,6 +946,39 @@
 				status = "disabled";
 			};
 		};
+
+		spi0: spi@4004ac00 {
+			compatible = "renesas,rz-rspi";
+			reg = <0x4004ac00 DT_SIZE_K(1)>;
+			interrupts = <413 1>, <414 1>, <415 1>;
+			interrupt-names = "rx", "tx", "error";
+			channel = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi1: spi@4004b000 {
+			compatible = "renesas,rz-rspi";
+			reg = <0x4004b000 DT_SIZE_K(1)>;
+			interrupts = <416 1>, <417 1>, <418 1>;
+			interrupt-names = "rx", "tx", "error";
+			channel = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi2: spi@4004b400 {
+			compatible = "renesas,rz-rspi";
+			reg = <0x4004b400 DT_SIZE_K(1)>;
+			interrupts = <419 1>, <420 1>, <421 1>;
+			interrupt-names = "rx", "tx", "error";
+			channel = <2>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
 	};
 };
 

diff --git a/samples/drivers/spi_bitbang/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.conf b/samples/drivers/spi_bitbang/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.conf
@@ -0,0 +1,3 @@
+CONFIG_GPIO=y
+CONFIG_SPI_RENESAS_RZ_RSPI_DMAC=n
+CONFIG_NO_OPTIMIZATIONS=y
diff --git a/samples/drivers/spi_bitbang/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay b/samples/drivers/spi_bitbang/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+spibb0: &spi1 {
+	cs-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.conf b/tests/drivers/spi/spi_loopback/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.conf
@@ -0,0 +1,7 @@
+CONFIG_SPI_ASYNC=y
+CONFIG_SPI_RENESAS_RZ_RSPI_INTERRUPT=y
+CONFIG_SPI_RENESAS_RZ_RSPI_DMAC=n
+CONFIG_SPI_RTIO=n
+CONFIG_SPI_LOOPBACK_MODE_LOOP=n
+CONFIG_SPI_LARGE_BUFFER_SIZE=2048
+CONFIG_SPI_IDEAL_TRANSFER_DURATION_SCALING=41
diff --git a/tests/drivers/spi/spi_loopback/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay b/tests/drivers/spi/spi_loopback/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi1 {
+	dmas = <&dma0 6 RZ_DMA_PERIPH_TO_MEM>,
+	       <&dma0 5 RZ_DMA_MEM_TO_PERIPH>;
+	dma-names = "rx", "tx";
+
+	slow@2 {
+		compatible = "test-spi-loopback-slow";
+		reg = <2>;
+		spi-max-frequency = <500000>;
+	};
+
+	fast@2 {
+		compatible = "test-spi-loopback-fast";
+		reg = <2>;
+		spi-max-frequency = <8333333>;
+	};
+};
+
+&dma0 {
+	status = "okay";
+	dma-buf-addr-alignment = <1>;
+};
diff --git a/west.yml b/west.yml
@@ -226,7 +226,7 @@ manifest:
         - hal
     - name: hal_renesas
       path: modules/hal/renesas
-      revision: d8ee5f18e95b9f4616a481be65e2c9ee0af1779f
+      revision: pull/148/head
       groups:
         - hal
     - name: hal_rpi_pico
-Original file line number
+Diff line change
@@ Expand Up / @@ -12,4 +12,5 @@ supported: @@
       - adc
       - i2c
       - mbox
+      - spi
     vendor: renesas