Add BLE support for MCXW23 SoC

boards/nxp/frdm_mcxw23/doc/index.rst

@@ -100,6 +100,16 @@ The MCXW23 SoC has 3 FLEXCOMM interfaces for serial
 communication. One is configured as USART for the console, one is
 configured for I2C, and the other one is configured for SPI.
 
+Fetch Binary Blobs
+******************
+
+To support Bluetooth, frdm_mcxw23 requires fetching controller lib blobs, which can be
+achieved by running the following command:
+
+.. code-block:: console
+
+   west blobs fetch hal_nxp
+
 Programming and Debugging
 *************************
 

boards/nxp/frdm_mcxw23/frdm_mcxw23_common.dtsi

@@ -16,6 +16,7 @@
 		zephyr,uart-mcumgr = &flexcomm0;
 		zephyr,console = &flexcomm0;
 		zephyr,shell-uart = &flexcomm0;
+		zephyr,uart-pipe = &flexcomm0;
 		zephyr,flash-controller = &iap;
 	};
 

boards/nxp/mcxw23_evk/doc/index.rst

@@ -79,6 +79,16 @@ The MCXW23 SoC has 3 FLEXCOMM interfaces for serial
 communication. One is configured as USART for the console, one is
 configured for I2C, and the other one is not used.
 
+Fetch Binary Blobs
+******************
+
+To support Bluetooth, mcxw23_evk requires fetching controller lib blobs, which can be
+achieved by running the following command:
+
+.. code-block:: console
+
+   west blobs fetch hal_nxp
+
 Programming and Debugging
 *************************
 

boards/nxp/mcxw23_evk/mcxw23_evk_common.dtsi

@@ -16,6 +16,7 @@
 		zephyr,uart-mcumgr = &flexcomm0;
 		zephyr,console = &flexcomm0;
 		zephyr,shell-uart = &flexcomm0;
+		zephyr,uart-pipe = &flexcomm0;
 		zephyr,flash-controller = &iap;
 	};
 

dts/arm/nxp/nxp_mcxw23x_common.dtsi

@@ -18,6 +18,8 @@
 	};
 
 	chosen {
+		zephyr,nbu = &ble_ll;
+		zephyr,bt-hci = &hci;
 		zephyr,entropy = &trng;
 	};
 
@@ -150,7 +152,7 @@
 	rtc: rtc@2c000 {
 		compatible = "nxp,lpc-rtc";
 		reg = <0x2c000 0x1000>;
-		interrupts = <29 0>;
+		interrupts = <29 1>;
 		status = "okay";
 
 		rtc_highres: rtc_highres {
@@ -162,7 +164,7 @@
 	ctimer0: ctimer@8000 {
 		compatible = "nxp,lpc-ctimer";
 		reg = <0x8000 0x1000>;
-		interrupts = <10 0>;
+		interrupts = <10 1>;
 		status = "disabled";
 		clk-source = <3>;
 		clocks = <&syscon MCUX_CTIMER0_CLK>;
@@ -174,7 +176,7 @@
 	ctimer1: ctimer@9000 {
 		compatible = "nxp,lpc-ctimer";
 		reg = <0x9000 0x1000>;
-		interrupts = <11 0>;
+		interrupts = <11 1>;
 		status = "disabled";
 		clk-source = <3>;
 		clocks = <&syscon MCUX_CTIMER1_CLK>;
@@ -186,7 +188,7 @@
 	ctimer2: ctimer@28000 {
 		compatible = "nxp,lpc-ctimer";
 		reg = <0x28000 0x1000>;
-		interrupts = <36 0>;
+		interrupts = <36 1>;
 		status = "disabled";
 		clk-source = <3>;
 		clocks = <&syscon MCUX_CTIMER2_CLK>;
@@ -198,7 +200,7 @@
 	ctimer3: ctimer@29000 {
 		compatible = "nxp,lpc-ctimer";
 		reg = <0x29000 0x1000>;
-		interrupts = <13 0>;
+		interrupts = <13 1>;
 		status = "disabled";
 		clk-source = <3>;
 		clocks = <&syscon MCUX_CTIMER3_CLK>;
@@ -210,7 +212,7 @@
 	ctimer4: ctimer@2a000 {
 		compatible = "nxp,lpc-ctimer";
 		reg = <0x2a000 0x1000>;
-		interrupts = <37 0>;
+		interrupts = <37 1>;
 		status = "disabled";
 		clk-source = <3>;
 		clocks = <&syscon MCUX_CTIMER4_CLK>;
@@ -222,7 +224,7 @@
 	flexcomm0: flexcomm@86000 {
 		compatible = "nxp,lpc-flexcomm";
 		reg = <0x86000 0x1000>;
-		interrupts = <14 0>;
+		interrupts = <14 1>;
 		clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
 		resets = <&reset NXP_SYSCON_RESET(1, 11)>;
 		status = "disabled";
@@ -231,7 +233,7 @@
 	flexcomm1: flexcomm@87000 {
 		compatible = "nxp,lpc-flexcomm";
 		reg = <0x87000 0x1000>;
-		interrupts = <15 0>;
+		interrupts = <15 1>;
 		clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
 		resets = <&reset NXP_SYSCON_RESET(1, 12)>;
 		status = "disabled";
@@ -240,7 +242,7 @@
 	flexcomm2: flexcomm@88000 {
 		compatible = "nxp,lpc-flexcomm";
 		reg = <0x88000 0x1000>;
-		interrupts = <16 0>;
+		interrupts = <16 1>;
 		clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
 		resets = <&reset NXP_SYSCON_RESET(1, 13)>;
 		status = "disabled";
@@ -250,13 +252,13 @@
 		compatible = "nxp,kinetis-trng";
 		reg = <0x3a000 0x1000>;
 		status = "okay";
-		interrupts = <53 0>;
+		interrupts = <53 1>;
 	};
 
 	dma0: dma-controller@82000 {
 		compatible = "nxp,lpc-dma";
 		reg = <0x82000 0x1000>;
-		interrupts = <1 0>;
+		interrupts = <1 1>;
 		dma-channels = <23>;
 		status = "disabled";
 		#dma-cells = <1>;
@@ -265,7 +267,7 @@
 	dma1: dma-controller@a7000 {
 		compatible = "nxp,lpc-dma";
 		reg = <0xa7000 0x1000>;
-		interrupts = <58 0>;
+		interrupts = <58 1>;
 		dma-channels = <10>;
 		status = "disabled";
 		#dma-cells = <1>;
@@ -274,10 +276,20 @@
 	wwdt0: watchdog@c000 {
 		compatible = "nxp,lpc-wwdt";
 		reg = <0xc000 0x1000>;
-		interrupts = <0 0>;
+		interrupts = <0 1>;
 		status = "disabled";
 		clk-divider = <1>;
 	};
+
+	hci: hci_ble {
+		compatible = "nxp,hci-ble";
+	};
+
+	ble_ll: ble_controller {
+		compatible = "nxp,nbu";
+		interrupts = <22 0>;
+		interrupt-names = "nbu_rx_int";
+	};
 };
 
 &nvic {

modules/hal_nxp/mcux/mcux-sdk-ng/components/components.cmake

@@ -30,14 +30,14 @@ if(CONFIG_NXP_RF_IMU)
     set(CONFIG_MCUX_COMPONENT_driver.gdma ON)
     set(CONFIG_MCUX_COMPONENT_component.wireless_imu_adapter ON)
     set(CONFIG_MCUX_PRJSEG_component.osa_interface.osa_macro_used ON)
-  elseif(CONFIG_SOC_FAMILY_MCXW)
+  elseif(CONFIG_SOC_SERIES_MCXW7XX)
     set(CONFIG_MCUX_COMPONENT_component.lists ON)
     set(CONFIG_MCUX_COMPONENT_component.rpmsg_adapter ON)
     zephyr_compile_definitions(HAL_RPMSG_SELECT_ROLE=0U)
   endif()
 endif()
 
-if(CONFIG_SOC_FAMILY_MCXW AND CONFIG_IEEE802154)
+if(CONFIG_SOC_SERIES_MCXW7XX AND CONFIG_IEEE802154)
   set(CONFIG_MCUX_COMPONENT_driver.spc ON)
   set(CONFIG_MCUX_COMPONENT_component.lists ON)
   set(CONFIG_USE_component_osa_zephyr ON)
@@ -51,7 +51,7 @@ if(CONFIG_USE_component_osa_zephyr)
 endif()
 
 # Component definitions
-if(CONFIG_NXP_RF_IMU AND CONFIG_SOC_FAMILY_MCXW)
+if(CONFIG_NXP_RF_IMU AND CONFIG_SOC_SERIES_MCXW7XX)
   zephyr_compile_definitions(HAL_RPMSG_SELECT_ROLE=0U)
 endif()
 

modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake

@@ -185,7 +185,7 @@ if(CONFIG_SOC_FAMILY_MCXN OR CONFIG_SOC_FAMILY_MCXA)
   set(CONFIG_MCUX_COMPONENT_driver.mcx_spc ON)
 endif()
 
-if(CONFIG_BT_NXP AND CONFIG_SOC_FAMILY_MCXW OR CONFIG_IEEE802154_MCXW)
+if(CONFIG_BT_NXP AND CONFIG_SOC_SERIES_MCXW7XX OR CONFIG_IEEE802154_MCXW)
   set(CONFIG_MCUX_COMPONENT_driver.spc ON)
 endif()
 

soc/nxp/mcx/mcxw/CMakeLists.txt

@@ -3,3 +3,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 add_subdirectory(${SOC_SERIES})
+
+zephyr_sources_ifdef(CONFIG_NXP_NBU
+  ../../common/nxp_nbu.c
+  )

soc/nxp/mcx/mcxw/Kconfig.defconfig

@@ -8,52 +8,4 @@ if SOC_FAMILY_MCXW
 config CORTEX_M_SYSTICK
 	default n if MCUX_LPTMR_TIMER
 
-if BT
-
-config MAIN_STACK_SIZE
-	default 2560
-
-config BT_LONG_WQ_STACK_SIZE
-	default 2560
-
-config SYSTEM_WORKQUEUE_STACK_SIZE
-	default 2048
-
-config BT_BUF_EVT_RX_COUNT
-	default 16
-
-config BT_BUF_ACL_TX_COUNT
-	default 12 if SOC_MCXW727C
-	default 8 if SOC_MCXW716C
-
-if SHELL
-
-config SHELL_STACK_SIZE
-	default 4096
-
-endif # SHELL
-
-# Include intercore messaging component
-config NXP_RF_IMU
-	default y
-
-#  Set the controller's public identity using NXP vendor command
-config BT_HCI_SET_PUBLIC_ADDR
-	default y
-
-# HCI RX buffers are received in ISR context. RX messages
-# need to be queued and processed by a dedicated thread
-config HCI_NXP_RX_THREAD
-	default y
-
-endif # BT
-
-if IEEE802154
-
-# Include intercore messaging component
-config NXP_RF_IMU
-	default y
-
-endif # IEEE802154
-
 endif # SOC_FAMILY_MCXW

soc/nxp/mcx/mcxw/mcxw2xx/Kconfig.defconfig

@@ -16,4 +16,20 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config FLASH_FILL_BUFFER_SIZE
 	default 512
 
-endif
+if BT
+
+config FPU
+	default y
+
+config BT_BUF_ACL_TX_COUNT
+	default 8
+
+config BT_LONG_WQ_STACK_SIZE
+	default 2048
+
+config MAIN_STACK_SIZE
+	default 2048
+
+endif # BT
+
+endif # SOC_SERIES_MCXW2XX

soc/nxp/mcx/mcxw/mcxw2xx/soc.c

@@ -30,12 +30,25 @@
 
 /* System clock frequency */
 extern uint32_t SystemCoreClock;
+extern void nxp_nbu_init(void);
 
 #define CTIMER_CLOCK_SOURCE(node_id) \
 	TO_CTIMER_CLOCK_SOURCE(DT_CLOCKS_CELL(node_id, name), DT_PROP(node_id, clk_source))
 #define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val)
 #define TO_CLOCK_ATTACH_ID(inst, val) MUX_A(CM_CTIMERCLKSEL##inst, val)
 #define CTIMER_CLOCK_SETUP(node_id) CLOCK_AttachClk(CTIMER_CLOCK_SOURCE(node_id));
+/** 32KHz oscillator load in cap setting */
+#define OSC_CAP_IN_SETTING 5
+/** 32KHz oscillator load out cap setting */
+#define OSC_CAP_OUT_SETTING 5
+
+static void configure_32k_osc(void)
+{
+	/* Configure 32KHz xtal caps for use with RDM */
+	POWER_XTAL32K_ConfigureCaps(OSC_CAP_IN_SETTING, OSC_CAP_OUT_SETTING);
+	POWER_PeripheralPowerOn(kPOWERCFG_XTAL32K);
+	CLOCK_Select32kOscClkSrc(kCLOCK_Osc32kClockSrc_XTAL);
+}
 
 /**
  *
@@ -77,6 +90,8 @@ __weak void clock_init(void)
 
 	DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP)
 	DT_FOREACH_STATUS_OKAY(nxp_ctimer_pwm, CTIMER_CLOCK_SETUP)
+
+	configure_32k_osc();
 }
 
 #ifdef CONFIG_SOC_RESET_HOOK
@@ -107,4 +122,8 @@ void soc_early_init_hook(void)
 	/* Turn on PINT device*/
 	PINT_Init(PINT);
 #endif
+
+#ifdef CONFIG_BT
+	nxp_nbu_init();
+#endif
 }

soc/nxp/mcx/mcxw/mcxw2xx/soc.h

@@ -41,4 +41,6 @@
 #define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */
 #define IOCON_PIO_MODE_PULLUP   0x20u /*!<@brief Selects pull-up function */
 
+#define nbu_handler BLE_LL_IRQHandler
+
 #endif /* _SOC__H_ */

soc/nxp/mcx/mcxw/mcxw7xx/CMakeLists.txt

@@ -6,10 +6,6 @@ zephyr_sources(soc.c)
 zephyr_sources_ifdef(CONFIG_SOC_MCXW716C mcxw71_platform_init.S)
 zephyr_sources_ifdef(CONFIG_SOC_MCXW727C mcxw72_platform_init.S)
 
-zephyr_sources_ifdef(CONFIG_NXP_NBU
-  ../../../common/nxp_nbu.c
-  )
-
 zephyr_include_directories(./)
 
 set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")