Add Zephyr support for Mediatek MT8365 platform

boards/mediatek/mt8365/Kconfig.mt8365

@@ -0,0 +1,5 @@
+# Copyright 2025 Mediatek
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MT8365
+	select SOC_MT8365

boards/mediatek/mt8365/afe-mt8365.dts

@@ -0,0 +1,111 @@
+/* Copyright 2025 Mediatek
+ * SPDX-License-Identifier: Apache-2.0
+ */
+afe_dl1: afe_dl1 {
+		compatible = "mediatek,afe";
+		afe-name = "DL1";
+		dai-id = <0>;
+		downlink;
+		base = <0x00000000 0x11220040>;
+		cur = <0x00000000 0x11220044>;
+		end = <0x00000000 0x11220048>;
+		fs = <0x11220014 0 4>;
+		mono = <0x11220014 21 1>;
+		enable = <0x11220010 1 1>;
+		hd = <0x112203d8 16 1>;
+	};
+
+	afe_dl2: afe_dl2 {
+		compatible = "mediatek,afe";
+		afe-name = "DL2";
+		dai-id = <1>;
+		downlink;
+		base = <0x00000000 0x11220050>;
+		cur = <0x00000000 0x11220054>;
+		end = <0x00000000 0x11220058>;
+		fs = <0x11220014 4 4>;
+		mono = <0x11220014 22 1>;
+		enable = <0x11220010 2 1>;
+		hd = <0x112203d8 18 1>;
+	};
+
+	afe_tdm_out: afe_tdm_out {
+		compatible = "mediatek,afe";
+		afe-name = "TDM_OUT";
+		dai-id = <4>;
+		downlink;
+		base = <0x00000000 0x11220374>;
+		cur = <0x00000000 0x11220378>;
+		end = <0x00000000 0x1122037c>;
+		enable = <0x11220370 0 1>;
+		hd = <0x112203d8 28 1>;
+	};
+
+	afe_awb: afe_awb {
+		compatible = "mediatek,afe";
+		afe-name = "AWB";
+		dai-id = <2>;
+		base = <0x00000000 0x11220070>;
+		cur = <0x00000000 0x1122007c>;
+		end = <0x00000000 0x11220078>;
+		fs = <0x11220014 12 4>;
+		mono = <0x11220014 24 1>;
+		enable = <0x11220010 6 1>;
+		hd = <0x112203d8 20 1>;
+		msb = <0x112200cc 17 1>;
+	};
+
+	afe_vul: afe_vul {
+		compatible = "mediatek,afe";
+		afe-name = "VUL";
+		dai-id = <3>;
+		base = <0x00000000 0x11220080>;
+		cur = <0x00000000 0x1122008c>;
+		end = <0x00000000 0x11220088>;
+		fs = <0x11220014 16 4>;
+		mono = <0x11220014 27 1>;
+		enable = <0x11220010 3 1>;
+		hd = <0x112203d8 22 1>;
+		msb = <0x112200cc 20 1>;
+	};
+
+	afe_vul2: afe_vul2 {
+		compatible = "mediatek,afe";
+		afe-name = "VUL2";
+		dai-id = <5>;
+		base = <0x00000000 0x11220350>;
+		cur = <0x00000000 0x1122035c>;
+		end = <0x00000000 0x11220358>;
+		fs = <0x11220010 20 4>;
+		mono = <0x11220010 10 1>;
+		enable = <0x11220010 9 1>;
+		hd = <0x112203d8 14 1>;
+		msb = <0x112200cc 21 1>;
+	};
+
+	afe_vul3: afe_vul3 {
+		compatible = "mediatek,afe";
+		afe-name = "VUL3";
+		dai-id = <6>;
+		base = <0x00000000 0x112208c0>;
+		cur = <0x00000000 0x112208c4>;
+		end = <0x00000000 0x112208c8>;
+		fs = <0x11220014 8 4>;
+		mono = <0x11220010 13 1>;
+		enable = <0x11220010 12 1>;
+		hd = <0x112203ec 10 1>;
+		msb = <0x112200cc 27 1>;
+	};
+
+	afe_tdm_in: afe_tdm_in {
+		compatible = "mediatek,afe";
+		afe-name = "TDM_IN";
+		dai-id = <7>;
+		base = <0x00000000 0x112209c4>;
+		cur = <0x00000000 0x112209cc>;
+		end = <0x00000000 0x112209c8>;
+		mono = <0x112209c0 1 1>;
+		enable = <0x112209c0 0 1>;
+		hd = <0x112203ec 8 1>;
+		msb = <0x112200cc 28 1>;
+	};

boards/mediatek/mt8365/board.yml

@@ -0,0 +1,6 @@
+boards:
+  - name: mt8365
+    full_name: MT8365 ADSP
+    vendor: mediatek
+    socs:
+      - name: mt8365

boards/mediatek/mt8365/mt8365_adsp.dts

@@ -0,0 +1,80 @@
+/* Copyright 2025 Mediatek
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+
+/dts-v1/;
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	sram1: memory@1e000000 {
+		 device_type = "memory";
+		 compatible = "mmio-sram";
+		 reg = <0x1e000000 DT_SIZE_K(416)>;
+	};
+
+	sram0: memory@40020000 {
+		 device_type = "memory";
+		 compatible = "mmio-sram";
+		 reg = <0x40020000 DT_SIZE_K(256)>;
+	};
+
+	dram0: memory@60000000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x60000000 DT_SIZE_K(13824)>;
+	};
+
+	dram1: memory@60d80000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x60d80000 DT_SIZE_K(2560)>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		core_intc: core_intc@0 {
+			compatible = "cdns,xtensa-core-intc";
+			reg = <0 4>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		intc1: intc@1d062130 {
+			compatible = "mediatek,adsp_intc";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			reg = <0x1d062130 4>;
+			status-reg = <0x1d062150>;
+			interrupts = <1 0 0>;
+			mask = <0x3ff>;
+			interrupt-parent = <&core_intc>;
+		};
+
+		ostimer64: ostimer64@1d060000 {
+			compatible = "mediatek,ostimer64";
+			reg = <0x1d060000 30>;
+		};
+
+		ostimer0: ostimer@1d060040 {
+			compatible = "mediatek,ostimer";
+			reg = <0x1d060040 8>;
+			interrupt-parent = <&core_intc>;
+			interrupts = <2 0 0>;
+		};
+
+		ipi: ipi@1d062114 {
+			compatible = "mediatek,ipi";
+			reg = <0x1d062114 4>;
+			interrupt-parent = <&intc1>;
+			interrupts = < 9 0 0 >;
+		};
+
+/* Generated code for AFE devices */
+#include "afe-mt8365.dts"
+
+	}; /* soc */
+};

boards/mediatek/mt8365/mt8365_mt8365_adsp.yaml

@@ -0,0 +1,11 @@
+identifier: mt8365/mt8365/adsp
+name: Mediatek mt8365 Audio DSP
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+testing:
+  only_tags:
+    - kernel
+    - sof
+vendor: mediatek

boards/mediatek/twister.yaml

@@ -16,3 +16,5 @@ variants:
     name: MediaTek MT8186 Audio DSP
   mt8196/mt8196/adsp:
     name: MediaTek MT8196 Audio DSP
+  mt8365/mt8365/adsp:
+    name: MediaTek MT8365 Audio DSP

drivers/timer/mtk_adsp_timer.c

@@ -32,6 +32,8 @@ const int32_t z_sys_timer_irq_for_test = DT_IRQN(DT_NODELABEL(ostimer0));
  * slaved the same underlying clock -- they don't skew relative to
  * each other.
  */
+
+#ifndef CONFIG_SOC_MT8365
 struct mtk_ostimer {
 	unsigned int con;
 	unsigned int rst;
@@ -48,6 +50,19 @@ struct mtk_ostimer64 {
 	unsigned int tval_h;
 	unsigned int irq_ack;
 };
+#else
+struct mtk_ostimer {
+	unsigned int con;
+	unsigned int cur;
+};
+
+struct mtk_ostimer64 {
+	unsigned int cntcr;
+	unsigned int cntsr;
+	unsigned int cur_l;
+	unsigned int cur_h;
+};
+#endif
 
 #define OSTIMER64 (*(volatile struct mtk_ostimer64 *)OSTIMER64_BASE)
 
@@ -67,11 +82,22 @@ struct mtk_ostimer64 {
 #define OSTIMER_CON_CLKSRC_PCLK 0x30 /*  ~312 MHz experimentally */
 #endif
 
-#define OSTIMER_IRQ_ACK_ENABLE BIT(0)
+#if defined(CONFIG_SOC_MT8365)
+#define OSTIMER_CON_IRQ_ENABLE    BIT(1)
+#define OSTIMER_CON_IRQ_STA_CLEAR BIT(4) /*  read = status, write = clear */
+#else
+#define OSTIMER_IRQ_ACK_ENABLE BIT(0) /*  read = status, write = enable */
 #define OSTIMER_IRQ_ACK_CLEAR  BIT(5)
+#endif
 
 #define OST64_HZ 13000000U
+
+#ifdef CONFIG_SOC_MT8365
+#define OST_HZ 13000000U
+#else
 #define OST_HZ 26000000U
+#endif
+
 #define OST64_PER_TICK (OST64_HZ / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
 #define OST_PER_TICK (OST_HZ / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
 
@@ -91,11 +117,20 @@ uint64_t sys_clock_cycle_get_64(void)
 {
 	uint32_t l, h0, h1;
 
+#ifndef CONFIG_SOC_MT8365
 	do {
 		h0 = OSTIMER64.cur_h;
 		l  = OSTIMER64.cur_l;
 		h1 = OSTIMER64.cur_h;
 	} while (h0 != h1);
+#else
+	/* cur_h is only updated when the cur_l is read.
+	 * Always read cur_l before cur_h to get a valid 64-bit timestamp.
+	 */
+	l = OSTIMER64.cur_l;
+	h0 = OSTIMER64.cur_h;
+	(void)h1; /* silence the "unused variable" warning */
+#endif
 
 	return (((uint64_t)h0) << 32) | l;
 }
@@ -110,6 +145,7 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
 	/* Round up to tick boundary */
 	dt = ((dt + OST64_PER_TICK - 1) / OST64_PER_TICK) * OST64_PER_TICK;
 
+#ifndef CONFIG_SOC_MT8365
 	/* Convert to "fast" OSTIMER[0] cycles! */
 	uint32_t cyc = 2 * (dt - (uint32_t)(now - last_announce));
 
@@ -121,6 +157,12 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
 	OSTIMERS[0].irq_ack |= OSTIMER_IRQ_ACK_CLEAR;
 	OSTIMERS[0].irq_ack |= OSTIMER_IRQ_ACK_ENABLE;
 	OSTIMERS[0].con |= OSTIMER_CON_ENABLE;
+#else
+	uint32_t cyc = dt - (uint32_t)(now - last_announce);
+
+	OSTIMERS[0].cur = cyc;
+	OSTIMERS[0].con |= OSTIMER_CON_IRQ_ENABLE;
+#endif
 }
 
 uint32_t sys_clock_elapsed(void)
@@ -150,9 +192,14 @@ static void timer_isr(__maybe_unused void *arg)
 	 * sys_clock_set_timeout() is responsible for turning it back
 	 * on.
 	 */
+#ifndef CONFIG_SOC_MT8365
 	OSTIMERS[0].irq_ack |=  OSTIMER_IRQ_ACK_CLEAR;
 	OSTIMERS[0].con     &= ~OSTIMER_CON_ENABLE;
 	OSTIMERS[0].irq_ack &= ~OSTIMER_IRQ_ACK_ENABLE;
+#else
+	OSTIMERS[0].con     |= OSTIMER_CON_IRQ_STA_CLEAR;
+	OSTIMERS[0].con     &= ~OSTIMER_CON_IRQ_ENABLE;
+#endif
 
 	last_announce += ticks * OST64_PER_TICK;
 	sys_clock_announce(ticks);
@@ -169,18 +216,27 @@ static int mtk_adsp_timer_init(void)
 
 	/* Disable all timers */
 	for (int i = 0; i < 4; i++) {
+#ifndef CONFIG_SOC_MT8365
 		OSTIMERS[i].con &= ~OSTIMER_CON_ENABLE;
 		OSTIMERS[i].irq_ack |= OSTIMER_IRQ_ACK_CLEAR;
 		OSTIMERS[i].irq_ack &= ~OSTIMER_IRQ_ACK_ENABLE;
+#else
+		OSTIMERS[i].con = OSTIMER_CON_IRQ_STA_CLEAR | OSTIMER_CON_ENABLE;
+		OSTIMERS[i].con &= ~OSTIMER_CON_ENABLE;
+#endif
 	}
 
 	/* Set them up to use the same clock.  Note that OSTIMER64 has
 	 * a built-in divide by two (or it's configurable and I don't
 	 * know the register) and exposes a 13 MHz counter!
 	 */
+#ifndef CONFIG_SOC_MT8365
 	OSTIMERS[0].con = ((OSTIMERS[0].con & ~OSTIMER_CON_CLKSRC_MASK)
 			   | OSTIMER_CON_CLKSRC_26M);
 	OSTIMERS[0].con |= OSTIMER_CON_ENABLE;
+#else
+	OSTIMERS[0].con |= OSTIMER_CON_IRQ_ENABLE | OSTIMER_CON_ENABLE;
+#endif
 
 	/* Clock is free running and survives reset, doesn't start at zero */
 	last_announce = sys_clock_cycle_get_64();

soc/mediatek/mt8xxx/CMakeLists.txt

@@ -1,7 +1,10 @@
 # Copyright 2023 The ChromiumOS Authors
 # SPDX-License-Identifier: Apache-2.0
 
-zephyr_library_sources(soc.c irq.c mbox.c)
+zephyr_library_sources(soc.c irq.c)
+
+zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_MT8365 mbox.c)
+zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_MT8365 ipi.c)
 
 zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_MT8195 ${CONFIG_SOC}/cpuclk.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_MT8188 ${CONFIG_SOC}/cpuclk.c)

soc/mediatek/mt8xxx/Kconfig.defconfig

@@ -62,6 +62,7 @@ config XTENSA_CCOUNT_HZ
 	default 400000000 if SOC_MT8186
 	default 800000000 if SOC_MT8188
 	default 800000000 if SOC_MT8196
+	default 600000000 if SOC_MT8365
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default $(dt_node_int_prop_int,$(dt_nodelabel_path,ostimer64),freq-hz)
@@ -89,6 +90,7 @@ config SOC_TOOLCHAIN_NAME
 	default "mtk_mt8195_adsp" if SOC_SERIES_MT8195
 	default "mtk_mt818x_adsp" if SOC_SERIES_MT818X
 	default "mtk_mt8196_adsp" if SOC_SERIES_MT8196
+	default "mtk_mt8365_adsp" if SOC_SERIES_MT8365
 
 config XTENSA_RESET_VECTOR
 	default n