soc: renesas: ra: Add RENESAS_PN config to reflect the SoC information #96828
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Update hal_renesas revision to get the update_renesas_soc_info Signed-off-by: Khoa Nguyen <[email protected]>
Add invisible RENESAS_PN config to reflect the SoC hardware information and provide input for hal_renesas Signed-off-by: Khoa Nguyen <[email protected]>
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The following west manifest projects have changed revision in this Pull Request:
⛔ DNM label due to: 1 project with PR revision Note: This message is automatically posted and updated by the Manifest GitHub Action. |
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requested review from
andrzej-kaczmarek,
blauret,
duynguyenxa,
ioannis-karachalios,
KhiemNguyenT,
soburi,
thaoluonguw,
thenguyenyf and
ydamigos
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| - J (0x4a): Dual Core, MIPI DSI/CSI is not available | ||
| - K (0x4b): Dual Core, MIPI DSI/CSI is available | ||
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| config RENESAS_PN_NUMBER_OF_CORES |
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Because now we have the config for PN number core, the existing config of second core boot should be updated?
https://github.com/renesas/zephyr/blob/update_renesas_soc_info/soc/renesas/ra/Kconfig#L27-L45
| select XIP | ||
| select SOC_EARLY_INIT_HOOK | ||
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| if SOC_SERIES_RA4E2 |
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some MCUs (such as RA4E2) only have one flash size across all part numbers, but should we define a default RENESAS_PN_ROM_SIZE similar to other MCUs? This could help us maintain from HAL more effectively rather than keeping it fixed as it is now? https://github.com/renesas/hal_renesas/blob/update_renesas_soc_info/zephyr/ra/ra_cfg/fsp_cfg/bsp/ra4e2/bsp_mcu_device_pn_cfg.h#L11
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or should we use directly from flash size config?
Add invisible
RENESAS_PN_config to reflect the SoC hardware information and provide input forhal_renesas