Skip to content

Enable nxp micfil driver #96980

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 4 commits into
base: main
Choose a base branch
from
Open

Enable nxp micfil driver #96980

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
cbb0c3b
drivers: audio: Add NXP MICFIL driver
ZhaoxiangJin Sep 29, 2025
f8b314f
drivers: mcux_syscon: enable MICFIL clock control
ZhaoxiangJin Sep 29, 2025
0a8b754
board: frdm_mcxn236: Enable MICFIL on frdm_mcxn236
ZhaoxiangJin Sep 29, 2025
89c0ae7
samples: i2s_codec: Enable nxp micfil sample
ZhaoxiangJin Sep 29, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
23 changes: 18 additions & 5 deletions boards/nxp/frdm_mcxn236/board.c
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright 2024 NXP
* Copyright 2024-2025 NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/init.h>
Expand Down Expand Up @@ -103,20 +103,23 @@ void board_early_init_hook(void)

CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ);

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1))
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || \
DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1)) || \
DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(micfil))
/* < Set up PLL1 */
const pll_setup_t pll1_Setup = {
.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) |
SCG_SPLLCTRL_SELP(1U),
.pllndiv = SCG_SPLLNDIV_NDIV(25U),
.pllpdiv = SCG_SPLLPDIV_PDIV(10U),
.pllmdiv = SCG_SPLLMDIV_MDIV(256U),
.pllRate = 24576000U};
.pllRate = 24576000U
};

/* Configure PLL1 to the desired values */
CLOCK_SetPLL1Freq(&pll1_Setup);
/* Set PLL1 CLK0 divider to value 1 */
CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 1U);
/* Set PLL1 CLK0 divider to value 2, then the clock is 12288000Hz. */
CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 2U);
#endif

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm0))
Expand Down Expand Up @@ -160,6 +163,7 @@ void board_early_init_hook(void)

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0))
CLOCK_EnableClock(kCLOCK_Gpio0);
CLOCK_EnableClock(kCLOCK_Port0);
#endif

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
Expand Down Expand Up @@ -339,6 +343,15 @@ void board_early_init_hook(void)
CLOCK_EnableClock(kCLOCK_Sai1);
#endif

#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(micfil))
CLOCK_SetClkDiv(kCLOCK_DivMicfilFClk, 1U);
CLOCK_AttachClk(kPLL1_CLK0_to_MICFILF);
CLOCK_EnableClock(kCLOCK_Micfil);

PORT0->PCR[16] = 0x00001900;
PORT0->PCR[17] = 0x00001900;
#endif

/* Set SystemCoreClock variable. */
SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
}
14 changes: 12 additions & 2 deletions boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,8 +8,8 @@
&pinctrl {
pinmux_flexcomm0_lpuart: pinmux_flexcomm0_lpuart {
group0 {
pinmux = <FC0_P0_PIO0_16>,
<FC0_P1_PIO0_17>;
pinmux = <FC0_P2_PIO0_6>,
<FC0_P3_PIO0_7>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
Expand Down Expand Up @@ -233,4 +233,14 @@
input-enable;
};
};

pinmux_micfil: pinmux_micfil {
group0 {
pinmux = <PDM0_CLK_PIO0_16>,
<PDM0_DATA0_PIO0_17>;
drive-strength = "high";
slew-rate = "fast";
input-enable;
};
};
};
6 changes: 6 additions & 0 deletions boards/nxp/frdm_mcxn236/frdm_mcxn236.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -427,3 +427,9 @@ dvp_20pin_interface: &video_sdma {};
pinctrl-0 = <&pinmux_sai1>;
pinctrl-names = "default";
};

&micfil {
status = "okay";
pinctrl-0 = <&pinmux_micfil>;
pinctrl-names = "default";
};
1 change: 1 addition & 0 deletions drivers/audio/CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -16,3 +16,4 @@ zephyr_library_sources_ifdef(CONFIG_AUDIO_CODEC_CS43L22 cs43l22.c)
zephyr_library_sources_ifdef(CONFIG_AUDIO_CODEC_PCM1681 pcm1681.c)
zephyr_library_sources_ifdef(CONFIG_AUDIO_CODEC_MAX98091 max98091.c)
zephyr_library_sources_ifdef(CONFIG_AUDIO_DMIC_AMBIQ_PDM dmic_ambiq_pdm.c)
zephyr_library_sources_ifdef(CONFIG_AUDIO_DMIC_NXP_MICFIL dmic_nxp_micfil.c)
1 change: 1 addition & 0 deletions drivers/audio/Kconfig
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -67,6 +67,7 @@ source "drivers/audio/Kconfig.mpxxdtyy"
source "drivers/audio/Kconfig.dmic_pdm_nrfx"
source "drivers/audio/Kconfig.dmic_mcux"
source "drivers/audio/Kconfig.dmic_ambiq_pdm"
source "drivers/audio/Kconfig.dmic_nxp_micfil"

endif # AUDIO_DMIC

Expand Down
22 changes: 22 additions & 0 deletions drivers/audio/Kconfig.dmic_nxp_micfil
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,22 @@
# Copyright 2025 NXP
#
# SPDX-License-Identifier: Apache-2.0

config AUDIO_DMIC_NXP_MICFIL
bool "NXP MICFIL driver"
default y
depends on DT_HAS_NXP_MICFIL_ENABLED
select HAS_MCUX
select CLOCK_CONTROL
help
Enable NXP MICFIL driver.

if AUDIO_DMIC_NXP_MICFIL

config DMIC_NXP_MICFIL_QUEUE_SIZE
int "Message queue depth"
default 4
help
Depth of the message queue used to pass filled buffers to the app.

endif # AUDIO_DMIC_NXP_MICFIL
Loading
Loading